1843a7ee8SRaphael Assenat /* 2843a7ee8SRaphael Assenat * eco5.h - Header file for the 8D Technologies ECO5 board. 3843a7ee8SRaphael Assenat * 4843a7ee8SRaphael Assenat * Based on am3517evm.h 5843a7ee8SRaphael Assenat * Based on ti/evm/evm.h 6843a7ee8SRaphael Assenat * 7843a7ee8SRaphael Assenat * Copyright (C) 2011 8D Technologies inc. 8843a7ee8SRaphael Assenat * Copyright (C) 2009 Texas Instruments Incorporated 9843a7ee8SRaphael Assenat * 101a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 11843a7ee8SRaphael Assenat */ 12843a7ee8SRaphael Assenat 13843a7ee8SRaphael Assenat #ifndef _ECO5PK_H__ 14843a7ee8SRaphael Assenat #define _ECO5PK_H__ 15843a7ee8SRaphael Assenat 16843a7ee8SRaphael Assenat const omap3_sysinfo sysinfo = { 17843a7ee8SRaphael Assenat DDR_DISCRETE, 18843a7ee8SRaphael Assenat "ECO5 Board", 19843a7ee8SRaphael Assenat "NAND", 20843a7ee8SRaphael Assenat }; 21843a7ee8SRaphael Assenat 22843a7ee8SRaphael Assenat /* 23843a7ee8SRaphael Assenat * IEN - Input Enable 24843a7ee8SRaphael Assenat * IDIS - Input Disable 25843a7ee8SRaphael Assenat * PTD - Pull type Down 26843a7ee8SRaphael Assenat * PTU - Pull type Up 27843a7ee8SRaphael Assenat * DIS - Pull type selection is inactive 28843a7ee8SRaphael Assenat * EN - Pull type selection is active 29843a7ee8SRaphael Assenat * M0 - Mode 0 30843a7ee8SRaphael Assenat * The commented string gives the final mux configuration for that pin 31843a7ee8SRaphael Assenat */ 32843a7ee8SRaphael Assenat #define MUX_ECO5_PK() \ 33843a7ee8SRaphael Assenat /* SDRC */\ 34843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \ 35843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \ 36843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \ 37843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \ 38843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \ 39843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \ 40843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \ 41843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \ 42843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \ 43843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \ 44843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \ 45843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \ 46843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \ 47843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \ 48843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \ 49843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \ 50843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \ 51843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \ 52843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \ 53843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \ 54843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \ 55843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \ 56843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \ 57843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \ 58843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \ 59843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \ 60843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \ 61843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \ 62843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \ 63843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \ 64843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \ 65843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \ 66843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \ 67843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \ 68843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \ 69843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \ 70843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \ 71843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \ 72843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \ 73843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \ 74843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \ 75843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_CKE0), (M0)) \ 76843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_CKE1), (M0)) \ 77843a7ee8SRaphael Assenat MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \ 78843a7ee8SRaphael Assenat MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \ 79843a7ee8SRaphael Assenat /* GPMC */\ 80843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \ 81843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \ 82843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \ 83843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \ 84843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \ 85843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \ 86843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \ 87843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \ 88843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \ 89843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \ 90843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \ 91843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \ 92843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \ 93843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \ 94843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \ 95843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \ 96843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \ 97843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \ 98843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \ 99843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \ 100843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \ 101843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \ 102843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \ 103843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \ 104843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \ 105843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \ 106843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \ 107843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) \ 108843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) \ 109843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) \ 110843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)) \ 111843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M3)) \ 112843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) \ 113843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | DIS | M4)) \ 114843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \ 115843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \ 116843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \ 117843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \ 118843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \ 119843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \ 120843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \ 121843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \ 122843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) \ 123843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) \ 124843a7ee8SRaphael Assenat /* - ETH_nRESET*/\ 125843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) \ 126843a7ee8SRaphael Assenat /* DSS */\ 127843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \ 128843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \ 129843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \ 130843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \ 131843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA0), (IEN | PTD | DIS | M4)) \ 132843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA1), (IEN | PTD | DIS | M4)) \ 133843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA2), (IEN | PTD | DIS | M4)) \ 134843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA3), (IEN | PTD | DIS | M4)) \ 135843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA4), (IEN | PTD | DIS | M4)) \ 136843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA5), (IEN | PTD | DIS | M4)) \ 137843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA6), (IEN | PTD | DIS | M4)) \ 138843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA7), (IEN | PTD | DIS | M4)) \ 139843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA8), (IDIS | PTU | EN | M4)) \ 140843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA9), (IDIS | PTU | EN | M4)) \ 141843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA10), (IDIS | PTU | EN | M4)) \ 142843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA11), (IDIS | PTU | EN | M4)) \ 143843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA12), (IDIS | PTU | EN | M4)) \ 144843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | EN | M4)) \ 145843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | EN | M4)) \ 146843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA15), (IDIS | PTU | EN | M4)) \ 147843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA16), (IDIS | PTU | EN | M4)) \ 148843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | EN | M4)) \ 149843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \ 150843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \ 151843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \ 152843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \ 153843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \ 154843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \ 155843a7ee8SRaphael Assenat /* CAMERA */\ 156843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \ 157843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \ 158843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \ 159843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \ 160843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\ 161843a7ee8SRaphael Assenat /* - CAM_RESET*/\ 162843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \ 163843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \ 164843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \ 165843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \ 166843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \ 167843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \ 168843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \ 169843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \ 170843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \ 171843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \ 172843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \ 173843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \ 174843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \ 175843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ 176843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \ 177843a7ee8SRaphael Assenat MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \ 178843a7ee8SRaphael Assenat MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \ 179843a7ee8SRaphael Assenat MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \ 180843a7ee8SRaphael Assenat MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \ 181843a7ee8SRaphael Assenat /* MMC */\ 182843a7ee8SRaphael Assenat MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \ 183843a7ee8SRaphael Assenat MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \ 184843a7ee8SRaphael Assenat MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \ 185843a7ee8SRaphael Assenat MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \ 186843a7ee8SRaphael Assenat MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \ 187843a7ee8SRaphael Assenat MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \ 188843a7ee8SRaphael Assenat MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \ 189843a7ee8SRaphael Assenat MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \ 190843a7ee8SRaphael Assenat MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \ 191843a7ee8SRaphael Assenat MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \ 192843a7ee8SRaphael Assenat \ 193843a7ee8SRaphael Assenat MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M0)) \ 194843a7ee8SRaphael Assenat MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M0)) \ 195843a7ee8SRaphael Assenat MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M0)) \ 196843a7ee8SRaphael Assenat MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | DIS | M0)) \ 197843a7ee8SRaphael Assenat MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | DIS | M0)) \ 198843a7ee8SRaphael Assenat MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | DIS | M0)) \ 199843a7ee8SRaphael Assenat /* McBSP */\ 200843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \ 201843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \ 202843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \ 203843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \ 204843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \ 205843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \ 206843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \ 207843a7ee8SRaphael Assenat \ 208843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) \ 209843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) \ 210843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) \ 211843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) \ 212843a7ee8SRaphael Assenat \ 213843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) \ 214843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) \ 215843a7ee8SRaphael Assenat \ 216843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /* LED ACT */ \ 217843a7ee8SRaphael Assenat \ 218843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) \ 219843a7ee8SRaphael Assenat \ 220843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_152*/\ 221843a7ee8SRaphael Assenat /* - LCD_INI*/\ 222843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\ 223843a7ee8SRaphael Assenat /* - LCD_ENVDD */\ 224843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\ 225843a7ee8SRaphael Assenat /* - LCD_QVGA/nVGA */\ 226843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_155*/\ 227843a7ee8SRaphael Assenat /* - LCD_RESB */\ 228843a7ee8SRaphael Assenat /* UART */\ 229843a7ee8SRaphael Assenat MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \ 230843a7ee8SRaphael Assenat MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \ 231843a7ee8SRaphael Assenat MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \ 232843a7ee8SRaphael Assenat \ 233843a7ee8SRaphael Assenat MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \ 234843a7ee8SRaphael Assenat MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \ 235843a7ee8SRaphael Assenat MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \ 236843a7ee8SRaphael Assenat MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \ 237843a7ee8SRaphael Assenat MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \ 238843a7ee8SRaphael Assenat \ 239843a7ee8SRaphael Assenat MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \ 240843a7ee8SRaphael Assenat MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \ 241843a7ee8SRaphael Assenat MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \ 242843a7ee8SRaphael Assenat MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \ 243843a7ee8SRaphael Assenat /* I2C */\ 244843a7ee8SRaphael Assenat MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \ 245843a7ee8SRaphael Assenat MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \ 246843a7ee8SRaphael Assenat MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \ 247843a7ee8SRaphael Assenat MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \ 248843a7ee8SRaphael Assenat MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \ 249843a7ee8SRaphael Assenat MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \ 250843a7ee8SRaphael Assenat MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \ 251843a7ee8SRaphael Assenat MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \ 252843a7ee8SRaphael Assenat /* McSPI */\ 253843a7ee8SRaphael Assenat MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \ 254843a7ee8SRaphael Assenat MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \ 255843a7ee8SRaphael Assenat MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \ 256843a7ee8SRaphael Assenat MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \ 257843a7ee8SRaphael Assenat MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\ 258843a7ee8SRaphael Assenat MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176*/\ 259843a7ee8SRaphael Assenat /* - LAN_INTR*/\ 260843a7ee8SRaphael Assenat MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) \ 261843a7ee8SRaphael Assenat \ 262843a7ee8SRaphael Assenat MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \ 263843a7ee8SRaphael Assenat MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \ 264843a7ee8SRaphael Assenat MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \ 265843a7ee8SRaphael Assenat MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \ 266843a7ee8SRaphael Assenat /* LCD_EN_BACKLIGHT */\ 267843a7ee8SRaphael Assenat MUX_VAL(CP(MCSPI2_CS1), (IDIS | PTD | EN | M4)) \ 268843a7ee8SRaphael Assenat /* CCDC */\ 269843a7ee8SRaphael Assenat MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0)) \ 270843a7ee8SRaphael Assenat MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1)) \ 271843a7ee8SRaphael Assenat MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0)) \ 272843a7ee8SRaphael Assenat MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0)) \ 273843a7ee8SRaphael Assenat MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1)) \ 274843a7ee8SRaphael Assenat MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0)) \ 275843a7ee8SRaphael Assenat MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0)) \ 276843a7ee8SRaphael Assenat MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0)) \ 277843a7ee8SRaphael Assenat MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0)) \ 278843a7ee8SRaphael Assenat MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0)) \ 279843a7ee8SRaphael Assenat MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0)) \ 280843a7ee8SRaphael Assenat MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0)) \ 281843a7ee8SRaphael Assenat MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0)) \ 282843a7ee8SRaphael Assenat /* RMII */\ 283843a7ee8SRaphael Assenat MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \ 284843a7ee8SRaphael Assenat MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \ 285843a7ee8SRaphael Assenat MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \ 286843a7ee8SRaphael Assenat MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \ 287843a7ee8SRaphael Assenat MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \ 288843a7ee8SRaphael Assenat MUX_VAL(CP(RMII_RXER), (PTD | M0)) \ 289843a7ee8SRaphael Assenat MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \ 290843a7ee8SRaphael Assenat MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \ 291843a7ee8SRaphael Assenat MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \ 292843a7ee8SRaphael Assenat MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \ 293843a7ee8SRaphael Assenat /* HECC */\ 294843a7ee8SRaphael Assenat MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \ 295843a7ee8SRaphael Assenat MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \ 296843a7ee8SRaphael Assenat /* HSUSB */\ 297843a7ee8SRaphael Assenat MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \ 298843a7ee8SRaphael Assenat MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \ 299843a7ee8SRaphael Assenat MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \ 300843a7ee8SRaphael Assenat MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \ 301843a7ee8SRaphael Assenat MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \ 302843a7ee8SRaphael Assenat MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \ 303843a7ee8SRaphael Assenat MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \ 304843a7ee8SRaphael Assenat MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \ 305843a7ee8SRaphael Assenat MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \ 306843a7ee8SRaphael Assenat MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \ 307843a7ee8SRaphael Assenat MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \ 308843a7ee8SRaphael Assenat MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \ 309843a7ee8SRaphael Assenat MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \ 310843a7ee8SRaphael Assenat /* HDQ */\ 311843a7ee8SRaphael Assenat MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) \ 312843a7ee8SRaphael Assenat /* Control and debug */\ 313843a7ee8SRaphael Assenat MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \ 314843a7ee8SRaphael Assenat MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \ 315843a7ee8SRaphael Assenat MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \ 316843a7ee8SRaphael Assenat /* SYS_nRESWARM */\ 317843a7ee8SRaphael Assenat MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \ 318843a7ee8SRaphael Assenat /* - GPIO30 */\ 319843a7ee8SRaphael Assenat MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /* GPIO_2 */\ 320843a7ee8SRaphael Assenat /* - PEN_IRQ */\ 321843a7ee8SRaphael Assenat MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /* GPIO_3 */\ 322843a7ee8SRaphael Assenat MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */\ 323843a7ee8SRaphael Assenat MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /* GPIO_5 */\ 324843a7ee8SRaphael Assenat MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\ 325843a7ee8SRaphael Assenat MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\ 326843a7ee8SRaphael Assenat MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /* GPIO_8 */\ 327843a7ee8SRaphael Assenat /* - VIO_1V8*/\ 328843a7ee8SRaphael Assenat MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \ 329843a7ee8SRaphael Assenat MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \ 330843a7ee8SRaphael Assenat \ 331843a7ee8SRaphael Assenat MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \ 332843a7ee8SRaphael Assenat MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \ 333843a7ee8SRaphael Assenat MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \ 334843a7ee8SRaphael Assenat /* JTAG */\ 335*b5ff205cSIgor Grinberg MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \ 336843a7ee8SRaphael Assenat MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \ 337843a7ee8SRaphael Assenat MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \ 338843a7ee8SRaphael Assenat MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \ 339843a7ee8SRaphael Assenat MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) \ 340843a7ee8SRaphael Assenat MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) \ 341843a7ee8SRaphael Assenat /* ETK (ES2 onwards) */\ 342843a7ee8SRaphael Assenat MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)) \ 343843a7ee8SRaphael Assenat MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)) \ 344843a7ee8SRaphael Assenat MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)) \ 345843a7ee8SRaphael Assenat MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)) \ 346843a7ee8SRaphael Assenat MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)) \ 347843a7ee8SRaphael Assenat MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)) \ 348843a7ee8SRaphael Assenat MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)) \ 349843a7ee8SRaphael Assenat MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)) \ 350843a7ee8SRaphael Assenat MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)) \ 351843a7ee8SRaphael Assenat MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)) \ 352843a7ee8SRaphael Assenat MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)) \ 353843a7ee8SRaphael Assenat MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)) \ 354843a7ee8SRaphael Assenat MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)) \ 355843a7ee8SRaphael Assenat MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)) \ 356843a7ee8SRaphael Assenat MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)) \ 357843a7ee8SRaphael Assenat MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)) \ 358843a7ee8SRaphael Assenat MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)) \ 359843a7ee8SRaphael Assenat MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)) \ 360843a7ee8SRaphael Assenat /* Die to Die */\ 361843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \ 362843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \ 363843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \ 364843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \ 365843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \ 366843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \ 367843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \ 368843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \ 369843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \ 370843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \ 371843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \ 372843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \ 373843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \ 374843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \ 375843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \ 376843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \ 377843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \ 378843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \ 379843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \ 380843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \ 381843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \ 382843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \ 383843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \ 384843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \ 385843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \ 386843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \ 387843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \ 388843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \ 389843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \ 390843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) 391843a7ee8SRaphael Assenat 392843a7ee8SRaphael Assenat #endif 393