1*843a7ee8SRaphael Assenat /* 2*843a7ee8SRaphael Assenat * eco5.h - Header file for the 8D Technologies ECO5 board. 3*843a7ee8SRaphael Assenat * 4*843a7ee8SRaphael Assenat * Based on am3517evm.h 5*843a7ee8SRaphael Assenat * Based on ti/evm/evm.h 6*843a7ee8SRaphael Assenat * 7*843a7ee8SRaphael Assenat * Copyright (C) 2011 8D Technologies inc. 8*843a7ee8SRaphael Assenat * Copyright (C) 2009 Texas Instruments Incorporated 9*843a7ee8SRaphael Assenat * 10*843a7ee8SRaphael Assenat * This program is free software; you can redistribute it and/or modify 11*843a7ee8SRaphael Assenat * it under the terms of the GNU General Public License as published by 12*843a7ee8SRaphael Assenat * the Free Software Foundation; either version 2 of the License, or 13*843a7ee8SRaphael Assenat * (at your option) any later version. 14*843a7ee8SRaphael Assenat * 15*843a7ee8SRaphael Assenat * This program is distributed in the hope that it will be useful, 16*843a7ee8SRaphael Assenat * but WITHOUT ANY WARRANTY; without even the implied warranty of 17*843a7ee8SRaphael Assenat * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18*843a7ee8SRaphael Assenat * GNU General Public License for more details. 19*843a7ee8SRaphael Assenat * 20*843a7ee8SRaphael Assenat * You should have received a copy of the GNU General Public License 21*843a7ee8SRaphael Assenat * along with this program; if not, write to the Free Software 22*843a7ee8SRaphael Assenat * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23*843a7ee8SRaphael Assenat */ 24*843a7ee8SRaphael Assenat 25*843a7ee8SRaphael Assenat #ifndef _ECO5PK_H__ 26*843a7ee8SRaphael Assenat #define _ECO5PK_H__ 27*843a7ee8SRaphael Assenat 28*843a7ee8SRaphael Assenat const omap3_sysinfo sysinfo = { 29*843a7ee8SRaphael Assenat DDR_DISCRETE, 30*843a7ee8SRaphael Assenat "ECO5 Board", 31*843a7ee8SRaphael Assenat "NAND", 32*843a7ee8SRaphael Assenat }; 33*843a7ee8SRaphael Assenat 34*843a7ee8SRaphael Assenat /* 35*843a7ee8SRaphael Assenat * IEN - Input Enable 36*843a7ee8SRaphael Assenat * IDIS - Input Disable 37*843a7ee8SRaphael Assenat * PTD - Pull type Down 38*843a7ee8SRaphael Assenat * PTU - Pull type Up 39*843a7ee8SRaphael Assenat * DIS - Pull type selection is inactive 40*843a7ee8SRaphael Assenat * EN - Pull type selection is active 41*843a7ee8SRaphael Assenat * M0 - Mode 0 42*843a7ee8SRaphael Assenat * The commented string gives the final mux configuration for that pin 43*843a7ee8SRaphael Assenat */ 44*843a7ee8SRaphael Assenat #define MUX_ECO5_PK() \ 45*843a7ee8SRaphael Assenat /* SDRC */\ 46*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \ 47*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \ 48*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \ 49*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \ 50*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \ 51*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \ 52*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \ 53*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \ 54*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \ 55*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \ 56*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \ 57*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \ 58*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \ 59*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \ 60*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \ 61*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \ 62*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \ 63*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \ 64*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \ 65*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \ 66*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \ 67*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \ 68*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \ 69*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \ 70*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \ 71*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \ 72*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \ 73*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \ 74*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \ 75*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \ 76*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \ 77*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \ 78*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \ 79*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \ 80*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \ 81*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \ 82*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \ 83*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \ 84*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \ 85*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \ 86*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \ 87*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_CKE0), (M0)) \ 88*843a7ee8SRaphael Assenat MUX_VAL(CP(SDRC_CKE1), (M0)) \ 89*843a7ee8SRaphael Assenat MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \ 90*843a7ee8SRaphael Assenat MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \ 91*843a7ee8SRaphael Assenat /* GPMC */\ 92*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \ 93*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \ 94*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \ 95*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \ 96*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \ 97*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \ 98*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \ 99*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \ 100*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \ 101*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \ 102*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \ 103*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \ 104*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \ 105*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \ 106*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \ 107*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \ 108*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \ 109*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \ 110*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \ 111*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \ 112*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \ 113*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \ 114*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \ 115*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \ 116*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \ 117*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \ 118*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \ 119*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) \ 120*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) \ 121*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) \ 122*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)) \ 123*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M3)) \ 124*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) \ 125*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | DIS | M4)) \ 126*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) \ 127*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \ 128*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \ 129*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \ 130*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \ 131*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) \ 132*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \ 133*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \ 134*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) \ 135*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) \ 136*843a7ee8SRaphael Assenat /* - ETH_nRESET*/\ 137*843a7ee8SRaphael Assenat MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) \ 138*843a7ee8SRaphael Assenat /* DSS */\ 139*843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \ 140*843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \ 141*843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \ 142*843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \ 143*843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA0), (IEN | PTD | DIS | M4)) \ 144*843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA1), (IEN | PTD | DIS | M4)) \ 145*843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA2), (IEN | PTD | DIS | M4)) \ 146*843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA3), (IEN | PTD | DIS | M4)) \ 147*843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA4), (IEN | PTD | DIS | M4)) \ 148*843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA5), (IEN | PTD | DIS | M4)) \ 149*843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA6), (IEN | PTD | DIS | M4)) \ 150*843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA7), (IEN | PTD | DIS | M4)) \ 151*843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA8), (IDIS | PTU | EN | M4)) \ 152*843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA9), (IDIS | PTU | EN | M4)) \ 153*843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA10), (IDIS | PTU | EN | M4)) \ 154*843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA11), (IDIS | PTU | EN | M4)) \ 155*843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA12), (IDIS | PTU | EN | M4)) \ 156*843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | EN | M4)) \ 157*843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | EN | M4)) \ 158*843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA15), (IDIS | PTU | EN | M4)) \ 159*843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA16), (IDIS | PTU | EN | M4)) \ 160*843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | EN | M4)) \ 161*843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \ 162*843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \ 163*843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \ 164*843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \ 165*843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \ 166*843a7ee8SRaphael Assenat MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \ 167*843a7ee8SRaphael Assenat /* CAMERA */\ 168*843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \ 169*843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \ 170*843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \ 171*843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \ 172*843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\ 173*843a7ee8SRaphael Assenat /* - CAM_RESET*/\ 174*843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \ 175*843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \ 176*843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \ 177*843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \ 178*843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \ 179*843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \ 180*843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \ 181*843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \ 182*843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \ 183*843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \ 184*843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \ 185*843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \ 186*843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \ 187*843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ 188*843a7ee8SRaphael Assenat MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \ 189*843a7ee8SRaphael Assenat MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \ 190*843a7ee8SRaphael Assenat MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \ 191*843a7ee8SRaphael Assenat MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \ 192*843a7ee8SRaphael Assenat MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \ 193*843a7ee8SRaphael Assenat /* MMC */\ 194*843a7ee8SRaphael Assenat MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \ 195*843a7ee8SRaphael Assenat MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \ 196*843a7ee8SRaphael Assenat MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \ 197*843a7ee8SRaphael Assenat MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \ 198*843a7ee8SRaphael Assenat MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \ 199*843a7ee8SRaphael Assenat MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \ 200*843a7ee8SRaphael Assenat MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \ 201*843a7ee8SRaphael Assenat MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \ 202*843a7ee8SRaphael Assenat MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \ 203*843a7ee8SRaphael Assenat MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \ 204*843a7ee8SRaphael Assenat \ 205*843a7ee8SRaphael Assenat MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M0)) \ 206*843a7ee8SRaphael Assenat MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M0)) \ 207*843a7ee8SRaphael Assenat MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M0)) \ 208*843a7ee8SRaphael Assenat MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | DIS | M0)) \ 209*843a7ee8SRaphael Assenat MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | DIS | M0)) \ 210*843a7ee8SRaphael Assenat MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | DIS | M0)) \ 211*843a7ee8SRaphael Assenat /* McBSP */\ 212*843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \ 213*843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \ 214*843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \ 215*843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \ 216*843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \ 217*843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \ 218*843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \ 219*843a7ee8SRaphael Assenat \ 220*843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) \ 221*843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) \ 222*843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) \ 223*843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) \ 224*843a7ee8SRaphael Assenat \ 225*843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) \ 226*843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) \ 227*843a7ee8SRaphael Assenat \ 228*843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) /* LED ACT */ \ 229*843a7ee8SRaphael Assenat \ 230*843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) \ 231*843a7ee8SRaphael Assenat \ 232*843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_152*/\ 233*843a7ee8SRaphael Assenat /* - LCD_INI*/\ 234*843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\ 235*843a7ee8SRaphael Assenat /* - LCD_ENVDD */\ 236*843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\ 237*843a7ee8SRaphael Assenat /* - LCD_QVGA/nVGA */\ 238*843a7ee8SRaphael Assenat MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_155*/\ 239*843a7ee8SRaphael Assenat /* - LCD_RESB */\ 240*843a7ee8SRaphael Assenat /* UART */\ 241*843a7ee8SRaphael Assenat MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \ 242*843a7ee8SRaphael Assenat MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \ 243*843a7ee8SRaphael Assenat MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \ 244*843a7ee8SRaphael Assenat \ 245*843a7ee8SRaphael Assenat MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \ 246*843a7ee8SRaphael Assenat MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \ 247*843a7ee8SRaphael Assenat MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \ 248*843a7ee8SRaphael Assenat MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \ 249*843a7ee8SRaphael Assenat MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \ 250*843a7ee8SRaphael Assenat \ 251*843a7ee8SRaphael Assenat MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \ 252*843a7ee8SRaphael Assenat MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \ 253*843a7ee8SRaphael Assenat MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \ 254*843a7ee8SRaphael Assenat MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \ 255*843a7ee8SRaphael Assenat /* I2C */\ 256*843a7ee8SRaphael Assenat MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \ 257*843a7ee8SRaphael Assenat MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \ 258*843a7ee8SRaphael Assenat MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \ 259*843a7ee8SRaphael Assenat MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \ 260*843a7ee8SRaphael Assenat MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \ 261*843a7ee8SRaphael Assenat MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \ 262*843a7ee8SRaphael Assenat MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \ 263*843a7ee8SRaphael Assenat MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \ 264*843a7ee8SRaphael Assenat /* McSPI */\ 265*843a7ee8SRaphael Assenat MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \ 266*843a7ee8SRaphael Assenat MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \ 267*843a7ee8SRaphael Assenat MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \ 268*843a7ee8SRaphael Assenat MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \ 269*843a7ee8SRaphael Assenat MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\ 270*843a7ee8SRaphael Assenat MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176*/\ 271*843a7ee8SRaphael Assenat /* - LAN_INTR*/\ 272*843a7ee8SRaphael Assenat MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) \ 273*843a7ee8SRaphael Assenat \ 274*843a7ee8SRaphael Assenat MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \ 275*843a7ee8SRaphael Assenat MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \ 276*843a7ee8SRaphael Assenat MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \ 277*843a7ee8SRaphael Assenat MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \ 278*843a7ee8SRaphael Assenat /* LCD_EN_BACKLIGHT */\ 279*843a7ee8SRaphael Assenat MUX_VAL(CP(MCSPI2_CS1), (IDIS | PTD | EN | M4)) \ 280*843a7ee8SRaphael Assenat /* CCDC */\ 281*843a7ee8SRaphael Assenat MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0)) \ 282*843a7ee8SRaphael Assenat MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1)) \ 283*843a7ee8SRaphael Assenat MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0)) \ 284*843a7ee8SRaphael Assenat MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0)) \ 285*843a7ee8SRaphael Assenat MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1)) \ 286*843a7ee8SRaphael Assenat MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0)) \ 287*843a7ee8SRaphael Assenat MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0)) \ 288*843a7ee8SRaphael Assenat MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0)) \ 289*843a7ee8SRaphael Assenat MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0)) \ 290*843a7ee8SRaphael Assenat MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0)) \ 291*843a7ee8SRaphael Assenat MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0)) \ 292*843a7ee8SRaphael Assenat MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0)) \ 293*843a7ee8SRaphael Assenat MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0)) \ 294*843a7ee8SRaphael Assenat /* RMII */\ 295*843a7ee8SRaphael Assenat MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \ 296*843a7ee8SRaphael Assenat MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \ 297*843a7ee8SRaphael Assenat MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \ 298*843a7ee8SRaphael Assenat MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \ 299*843a7ee8SRaphael Assenat MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \ 300*843a7ee8SRaphael Assenat MUX_VAL(CP(RMII_RXER), (PTD | M0)) \ 301*843a7ee8SRaphael Assenat MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \ 302*843a7ee8SRaphael Assenat MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \ 303*843a7ee8SRaphael Assenat MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \ 304*843a7ee8SRaphael Assenat MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \ 305*843a7ee8SRaphael Assenat /* HECC */\ 306*843a7ee8SRaphael Assenat MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \ 307*843a7ee8SRaphael Assenat MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \ 308*843a7ee8SRaphael Assenat /* HSUSB */\ 309*843a7ee8SRaphael Assenat MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \ 310*843a7ee8SRaphael Assenat MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \ 311*843a7ee8SRaphael Assenat MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \ 312*843a7ee8SRaphael Assenat MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \ 313*843a7ee8SRaphael Assenat MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \ 314*843a7ee8SRaphael Assenat MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \ 315*843a7ee8SRaphael Assenat MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \ 316*843a7ee8SRaphael Assenat MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \ 317*843a7ee8SRaphael Assenat MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \ 318*843a7ee8SRaphael Assenat MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \ 319*843a7ee8SRaphael Assenat MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \ 320*843a7ee8SRaphael Assenat MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \ 321*843a7ee8SRaphael Assenat MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \ 322*843a7ee8SRaphael Assenat /* HDQ */\ 323*843a7ee8SRaphael Assenat MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) \ 324*843a7ee8SRaphael Assenat /* Control and debug */\ 325*843a7ee8SRaphael Assenat MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \ 326*843a7ee8SRaphael Assenat MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \ 327*843a7ee8SRaphael Assenat MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \ 328*843a7ee8SRaphael Assenat /* SYS_nRESWARM */\ 329*843a7ee8SRaphael Assenat MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | DIS | M4)) \ 330*843a7ee8SRaphael Assenat /* - GPIO30 */\ 331*843a7ee8SRaphael Assenat MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /* GPIO_2 */\ 332*843a7ee8SRaphael Assenat /* - PEN_IRQ */\ 333*843a7ee8SRaphael Assenat MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /* GPIO_3 */\ 334*843a7ee8SRaphael Assenat MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */\ 335*843a7ee8SRaphael Assenat MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /* GPIO_5 */\ 336*843a7ee8SRaphael Assenat MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\ 337*843a7ee8SRaphael Assenat MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\ 338*843a7ee8SRaphael Assenat MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /* GPIO_8 */\ 339*843a7ee8SRaphael Assenat /* - VIO_1V8*/\ 340*843a7ee8SRaphael Assenat MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \ 341*843a7ee8SRaphael Assenat MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \ 342*843a7ee8SRaphael Assenat \ 343*843a7ee8SRaphael Assenat MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \ 344*843a7ee8SRaphael Assenat MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \ 345*843a7ee8SRaphael Assenat MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \ 346*843a7ee8SRaphael Assenat /* JTAG */\ 347*843a7ee8SRaphael Assenat MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \ 348*843a7ee8SRaphael Assenat MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \ 349*843a7ee8SRaphael Assenat MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \ 350*843a7ee8SRaphael Assenat MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \ 351*843a7ee8SRaphael Assenat MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) \ 352*843a7ee8SRaphael Assenat MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) \ 353*843a7ee8SRaphael Assenat /* ETK (ES2 onwards) */\ 354*843a7ee8SRaphael Assenat MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)) \ 355*843a7ee8SRaphael Assenat MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)) \ 356*843a7ee8SRaphael Assenat MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M0)) \ 357*843a7ee8SRaphael Assenat MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M0)) \ 358*843a7ee8SRaphael Assenat MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M0)) \ 359*843a7ee8SRaphael Assenat MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M0)) \ 360*843a7ee8SRaphael Assenat MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)) \ 361*843a7ee8SRaphael Assenat MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)) \ 362*843a7ee8SRaphael Assenat MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)) \ 363*843a7ee8SRaphael Assenat MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)) \ 364*843a7ee8SRaphael Assenat MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)) \ 365*843a7ee8SRaphael Assenat MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)) \ 366*843a7ee8SRaphael Assenat MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)) \ 367*843a7ee8SRaphael Assenat MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)) \ 368*843a7ee8SRaphael Assenat MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)) \ 369*843a7ee8SRaphael Assenat MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)) \ 370*843a7ee8SRaphael Assenat MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)) \ 371*843a7ee8SRaphael Assenat MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)) \ 372*843a7ee8SRaphael Assenat /* Die to Die */\ 373*843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \ 374*843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \ 375*843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \ 376*843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \ 377*843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \ 378*843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \ 379*843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \ 380*843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \ 381*843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \ 382*843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \ 383*843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \ 384*843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \ 385*843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \ 386*843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \ 387*843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \ 388*843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \ 389*843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \ 390*843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \ 391*843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \ 392*843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \ 393*843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \ 394*843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \ 395*843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \ 396*843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \ 397*843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \ 398*843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \ 399*843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \ 400*843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \ 401*843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \ 402*843a7ee8SRaphael Assenat MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) 403*843a7ee8SRaphael Assenat 404*843a7ee8SRaphael Assenat #endif 405