1 /* 2 * Copyright (C) 2006 Tensilica Inc. 3 * Copyright (C) 2014 - 2016 Cadence Design Systems Inc. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _XTENSA_CACHEASM_H 9 #define _XTENSA_CACHEASM_H 10 11 #include <asm/cache.h> 12 #include <asm/asmmacro.h> 13 #include <linux/stringify.h> 14 15 #define PAGE_SIZE 4096 16 #define DCACHE_WAY_SIZE (XCHAL_DCACHE_SIZE/XCHAL_DCACHE_WAYS) 17 #define ICACHE_WAY_SIZE (XCHAL_ICACHE_SIZE/XCHAL_ICACHE_WAYS) 18 #define DCACHE_WAY_SHIFT (XCHAL_DCACHE_SETWIDTH + XCHAL_DCACHE_LINEWIDTH) 19 #define ICACHE_WAY_SHIFT (XCHAL_ICACHE_SETWIDTH + XCHAL_ICACHE_LINEWIDTH) 20 21 /* 22 * Define cache functions as macros here so that they can be used 23 * by the kernel and boot loader. We should consider moving them to a 24 * library that can be linked by both. 25 * 26 * Locking 27 * 28 * ___unlock_dcache_all 29 * ___unlock_icache_all 30 * 31 * Flush and invaldating 32 * 33 * ___flush_invalidate_dcache_{all|range|page} 34 * ___flush_dcache_{all|range|page} 35 * ___invalidate_dcache_{all|range|page} 36 * ___invalidate_icache_{all|range|page} 37 * 38 */ 39 40 .macro __loop_cache_all ar at insn size line_width 41 42 movi \ar, 0 43 44 __loopi \ar, \at, \size, (4 << (\line_width)) 45 46 \insn \ar, 0 << (\line_width) 47 \insn \ar, 1 << (\line_width) 48 \insn \ar, 2 << (\line_width) 49 \insn \ar, 3 << (\line_width) 50 51 __endla \ar, \at, 4 << (\line_width) 52 53 .endm 54 55 56 .macro __loop_cache_range ar as at insn line_width 57 58 extui \at, \ar, 0, \line_width 59 add \as, \as, \at 60 61 __loops \ar, \as, \at, \line_width 62 \insn \ar, 0 63 __endla \ar, \at, (1 << (\line_width)) 64 65 .endm 66 67 68 .macro __loop_cache_page ar at insn line_width 69 70 __loopi \ar, \at, PAGE_SIZE, 4 << (\line_width) 71 72 \insn \ar, 0 << (\line_width) 73 \insn \ar, 1 << (\line_width) 74 \insn \ar, 2 << (\line_width) 75 \insn \ar, 3 << (\line_width) 76 77 __endla \ar, \at, 4 << (\line_width) 78 79 .endm 80 81 82 .macro ___unlock_dcache_all ar at 83 84 #if XCHAL_DCACHE_LINE_LOCKABLE && XCHAL_DCACHE_SIZE 85 __loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH 86 #endif 87 88 .endm 89 90 91 .macro ___unlock_icache_all ar at 92 93 #if XCHAL_ICACHE_LINE_LOCKABLE && XCHAL_ICACHE_SIZE 94 __loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE XCHAL_ICACHE_LINEWIDTH 95 #endif 96 97 .endm 98 99 100 .macro ___flush_invalidate_dcache_all ar at 101 102 #if XCHAL_DCACHE_SIZE 103 __loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH 104 #endif 105 106 .endm 107 108 109 .macro ___flush_dcache_all ar at 110 111 #if XCHAL_DCACHE_SIZE 112 __loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH 113 #endif 114 115 .endm 116 117 118 .macro ___invalidate_dcache_all ar at 119 120 #if XCHAL_DCACHE_SIZE 121 __loop_cache_all \ar \at dii __stringify(DCACHE_WAY_SIZE) \ 122 XCHAL_DCACHE_LINEWIDTH 123 #endif 124 125 .endm 126 127 128 .macro ___invalidate_icache_all ar at 129 130 #if XCHAL_ICACHE_SIZE 131 __loop_cache_all \ar \at iii __stringify(ICACHE_WAY_SIZE) \ 132 XCHAL_ICACHE_LINEWIDTH 133 #endif 134 135 .endm 136 137 138 139 .macro ___flush_invalidate_dcache_range ar as at 140 141 #if XCHAL_DCACHE_SIZE 142 __loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH 143 #endif 144 145 .endm 146 147 148 .macro ___flush_dcache_range ar as at 149 150 #if XCHAL_DCACHE_SIZE 151 __loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH 152 #endif 153 154 .endm 155 156 157 .macro ___invalidate_dcache_range ar as at 158 159 #if XCHAL_DCACHE_SIZE 160 __loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH 161 #endif 162 163 .endm 164 165 166 .macro ___invalidate_icache_range ar as at 167 168 #if XCHAL_ICACHE_SIZE 169 __loop_cache_range \ar \as \at ihi XCHAL_ICACHE_LINEWIDTH 170 #endif 171 172 .endm 173 174 175 176 .macro ___flush_invalidate_dcache_page ar as 177 178 #if XCHAL_DCACHE_SIZE 179 __loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH 180 #endif 181 182 .endm 183 184 185 .macro ___flush_dcache_page ar as 186 187 #if XCHAL_DCACHE_SIZE 188 __loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH 189 #endif 190 191 .endm 192 193 194 .macro ___invalidate_dcache_page ar as 195 196 #if XCHAL_DCACHE_SIZE 197 __loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH 198 #endif 199 200 .endm 201 202 203 .macro ___invalidate_icache_page ar as 204 205 #if XCHAL_ICACHE_SIZE 206 __loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH 207 #endif 208 209 .endm 210 211 #endif /* _XTENSA_CACHEASM_H */ 212