1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */
2c978b524SChris Zankel /*
3c978b524SChris Zankel  * Based on Linux/Xtensa kernel version
4c978b524SChris Zankel  *
5c978b524SChris Zankel  * Copyright (C) 2001 - 2007 Tensilica Inc.
6c978b524SChris Zankel  */
7c978b524SChris Zankel 
8c978b524SChris Zankel #ifndef _XTENSA_BYTEORDER_H
9c978b524SChris Zankel #define _XTENSA_BYTEORDER_H
10c978b524SChris Zankel 
11c978b524SChris Zankel #include <asm/types.h>
12c978b524SChris Zankel 
___arch__swab32(__u32 x)13c978b524SChris Zankel static inline __attribute__((const)) __u32 ___arch__swab32(__u32 x)
14c978b524SChris Zankel {
15c978b524SChris Zankel 	__u32 res;
16c978b524SChris Zankel 
17c978b524SChris Zankel 	/* instruction sequence from Xtensa ISA release 2/2000 */
18c978b524SChris Zankel 	__asm__("ssai     8\n\t"
19c978b524SChris Zankel 		"srli     %0, %1, 16\n\t"
20c978b524SChris Zankel 		"src      %0, %0, %1\n\t"
21c978b524SChris Zankel 		"src      %0, %0, %0\n\t"
22c978b524SChris Zankel 		"src      %0, %1, %0\n"
23c978b524SChris Zankel 		: "=&a" (res)
24c978b524SChris Zankel 		: "a" (x)
25c978b524SChris Zankel 		);
26c978b524SChris Zankel 	return res;
27c978b524SChris Zankel }
28c978b524SChris Zankel 
___arch__swab16(__u16 x)29c978b524SChris Zankel static inline __attribute__((const)) __u16 ___arch__swab16(__u16 x)
30c978b524SChris Zankel {
31c978b524SChris Zankel 	/*
32c978b524SChris Zankel 	 * Given that 'short' values are signed (i.e., can be negative),
33c978b524SChris Zankel 	 * we cannot assume that the upper 16-bits of the register are
34c978b524SChris Zankel 	 * zero.  We are careful to mask values after shifting.
35c978b524SChris Zankel 	 */
36c978b524SChris Zankel 
37c978b524SChris Zankel 	/*
38c978b524SChris Zankel 	 * There exists an anomaly between xt-gcc and xt-xcc.  xt-gcc
39c978b524SChris Zankel 	 * inserts an extui instruction after putting this function inline
40c978b524SChris Zankel 	 * to ensure that it uses only the least-significant 16 bits of
41c978b524SChris Zankel 	 * the result.  xt-xcc doesn't use an extui, but assumes the
42c978b524SChris Zankel 	 * __asm__ macro follows convention that the upper 16 bits of an
43c978b524SChris Zankel 	 * 'unsigned short' result are still zero.  This macro doesn't
44c978b524SChris Zankel 	 * follow convention; indeed, it leaves garbage in the upport 16
45c978b524SChris Zankel 	 * bits of the register.
46c978b524SChris Zankel 	 *
47c978b524SChris Zankel 	 * Declaring the temporary variables 'res' and 'tmp' to be 32-bit
48c978b524SChris Zankel 	 * types while the return type of the function is a 16-bit type
49c978b524SChris Zankel 	 * forces both compilers to insert exactly one extui instruction
50c978b524SChris Zankel 	 * (or equivalent) to mask off the upper 16 bits.
51c978b524SChris Zankel 	 */
52c978b524SChris Zankel 
53c978b524SChris Zankel 	__u32 res;
54c978b524SChris Zankel 	__u32 tmp;
55c978b524SChris Zankel 
56c978b524SChris Zankel 	__asm__("extui    %1, %2, 8, 8\n\t"
57c978b524SChris Zankel 		"slli     %0, %2, 8\n\t"
58c978b524SChris Zankel 		"or       %0, %0, %1\n"
59c978b524SChris Zankel 		: "=&a" (res), "=&a" (tmp)
60c978b524SChris Zankel 		: "a" (x)
61c978b524SChris Zankel 		);
62c978b524SChris Zankel 
63c978b524SChris Zankel 	return res;
64c978b524SChris Zankel }
65c978b524SChris Zankel 
66c978b524SChris Zankel #define __arch__swab32(x) ___arch__swab32(x)
67c978b524SChris Zankel #define __arch__swab16(x) ___arch__swab16(x)
68c978b524SChris Zankel 
69c978b524SChris Zankel #if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
70c978b524SChris Zankel #  define __BYTEORDER_HAS_U64__
71c978b524SChris Zankel #  define __SWAB_64_THRU_32__
72c978b524SChris Zankel #endif
73c978b524SChris Zankel 
74c978b524SChris Zankel #ifdef __XTENSA_EL__
75c978b524SChris Zankel # include <linux/byteorder/little_endian.h>
76c978b524SChris Zankel #elif defined(__XTENSA_EB__)
77c978b524SChris Zankel # include <linux/byteorder/big_endian.h>
78c978b524SChris Zankel #else
79c978b524SChris Zankel # error processor byte order undefined!
80c978b524SChris Zankel #endif
81c978b524SChris Zankel 
82c978b524SChris Zankel #endif /* _XTENSA_BYTEORDER_H */
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