1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * This header file describes this specific Xtensa processor's TIE extensions 4 * that extend basic Xtensa core functionality. It is customized to this 5 * Xtensa processor configuration. 6 * This file is autogenerated, please do not edit. 7 * 8 * Copyright (C) 1999-2015 Cadence Design Systems Inc. 9 */ 10 11 #ifndef _XTENSA_CORE_TIE_H 12 #define _XTENSA_CORE_TIE_H 13 14 #define XCHAL_CP_NUM 0 /* number of coprocessors */ 15 #define XCHAL_CP_MAX 0 /* max CP ID + 1 (0 if none) */ 16 #define XCHAL_CP_MASK 0x00 /* bitmask of all CPs by ID */ 17 #define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ 18 19 /* Save area for non-coprocessor optional and custom (TIE) state: */ 20 #define XCHAL_NCP_SA_SIZE 28 21 #define XCHAL_NCP_SA_ALIGN 4 22 23 /* Total save area for optional and custom state (NCP + CPn): */ 24 #define XCHAL_TOTAL_SA_SIZE 32 /* with 16-byte align padding */ 25 #define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */ 26 27 /* 28 * Detailed contents of save areas. 29 * NOTE: caller must define the XCHAL_SA_REG macro (not defined here) 30 * before expanding the XCHAL_xxx_SA_LIST() macros. 31 * 32 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize, 33 * dbnum,base,regnum,bitsz,gapsz,reset,x...) 34 * 35 * s = passed from XCHAL_*_LIST(s), eg. to select how to expand 36 * ccused = set if used by compiler without special options or code 37 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global) 38 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg) 39 * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg) 40 * name = lowercase reg name (no quotes) 41 * galign = group byte alignment (power of 2) (galign >= align) 42 * align = register byte alignment (power of 2) 43 * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz) 44 * (not including any pad bytes required to galign this or next reg) 45 * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>) 46 * base = reg shortname w/o index (or sr=special, ur=TIE user reg) 47 * regnum = reg index in regfile, or special/TIE-user reg number 48 * bitsz = number of significant bits (regfile width, or ur/sr mask bits) 49 * gapsz = intervening bits, if bitsz bits not stored contiguously 50 * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize) 51 * reset = register reset value (or 0 if undefined at reset) 52 * x = reserved for future use (0 until then) 53 * 54 * To filter out certain registers, e.g. to expand only the non-global 55 * registers used by the compiler, you can do something like this: 56 * 57 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p) 58 * #define SELCC0(p...) 59 * #define SELCC1(abikind,p...) SELAK##abikind(p) 60 * #define SELAK0(p...) REG(p) 61 * #define SELAK1(p...) REG(p) 62 * #define SELAK2(p...) 63 * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \ 64 * ...what you want to expand... 65 */ 66 67 #define XCHAL_NCP_SA_NUM 7 68 #define XCHAL_NCP_SA_LIST(s) \ 69 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \ 70 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \ 71 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \ 72 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \ 73 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \ 74 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \ 75 XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) 76 77 #define XCHAL_CP0_SA_NUM 0 78 #define XCHAL_CP0_SA_LIST(s) /* empty */ 79 80 #define XCHAL_CP1_SA_NUM 0 81 #define XCHAL_CP1_SA_LIST(s) /* empty */ 82 83 #define XCHAL_CP2_SA_NUM 0 84 #define XCHAL_CP2_SA_LIST(s) /* empty */ 85 86 #define XCHAL_CP3_SA_NUM 0 87 #define XCHAL_CP3_SA_LIST(s) /* empty */ 88 89 #define XCHAL_CP4_SA_NUM 0 90 #define XCHAL_CP4_SA_LIST(s) /* empty */ 91 92 #define XCHAL_CP5_SA_NUM 0 93 #define XCHAL_CP5_SA_LIST(s) /* empty */ 94 95 #define XCHAL_CP6_SA_NUM 0 96 #define XCHAL_CP6_SA_LIST(s) /* empty */ 97 98 #define XCHAL_CP7_SA_NUM 0 99 #define XCHAL_CP7_SA_LIST(s) /* empty */ 100 101 /* Byte length of instruction from its first nibble (op0 field), per FLIX. */ 102 #define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3 103 /* Byte length of instruction from its first byte, per FLIX. */ 104 #define XCHAL_BYTE0_FORMAT_LENGTHS \ 105 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ 106 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ 107 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ 108 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ 109 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ 110 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ 111 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ 112 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3 113 114 #endif /*_XTENSA_CORE_TIE_H*/ 115 116