1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * This header file contains assembly-language definitions (assembly 4 * macros, etc.) for this specific Xtensa processor's TIE extensions 5 * and options. It is customized to this Xtensa processor configuration. 6 * This file is autogenerated, please do not edit. 7 * 8 * Copyright (C) 1999-2010 Tensilica Inc. 9 */ 10 11 #ifndef _XTENSA_CORE_TIE_ASM_H 12 #define _XTENSA_CORE_TIE_ASM_H 13 14 /* Selection parameter values for save-area save/restore macros: */ 15 /* Option vs. TIE: */ 16 #define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ 17 #define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ 18 #define XTHAL_SAS_ANYOT 0x0003 /* both of the above */ 19 /* Whether used automatically by compiler: */ 20 #define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ 21 #define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ 22 #define XTHAL_SAS_ANYCC 0x000C /* both of the above */ 23 /* ABI handling across function calls: */ 24 #define XTHAL_SAS_CALR 0x0010 /* caller-saved */ 25 #define XTHAL_SAS_CALE 0x0020 /* callee-saved */ 26 #define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ 27 #define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */ 28 /* Misc */ 29 #define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ 30 #define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \ 31 | ((ccuse) & XTHAL_SAS_ANYCC) \ 32 | ((abi) & XTHAL_SAS_ANYABI) ) 33 34 35 36 /* 37 * Macro to save all non-coprocessor (extra) custom TIE and optional state 38 * (not including zero-overhead loop registers). 39 * Required parameters: 40 * ptr Save area pointer address register (clobbered) 41 * (register must contain a 4 byte aligned address). 42 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS 43 * registers are clobbered, the remaining are unused). 44 * Optional parameters: 45 * continue If macro invoked as part of a larger store sequence, set to 1 46 * if this is not the first in the sequence. Defaults to 0. 47 * ofs Offset from start of larger sequence (from value of first ptr 48 * in sequence) at which to store. Defaults to next available space 49 * (or 0 if <continue> is 0). 50 * select Select what category(ies) of registers to store, as a bitmask 51 * (see XTHAL_SAS_xxx constants). Defaults to all registers. 52 * alloc Select what category(ies) of registers to allocate; if any 53 * category is selected here that is not in <select>, space for 54 * the corresponding registers is skipped without doing any store. 55 */ 56 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 57 xchal_sa_start \continue, \ofs 58 // Optional global register used by default by the compiler: 59 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) 60 xchal_sa_align \ptr, 0, 1020, 4, 4 61 rur.THREADPTR \at1 // threadptr option 62 s32i \at1, \ptr, .Lxchal_ofs_+0 63 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 64 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 65 xchal_sa_align \ptr, 0, 1020, 4, 4 66 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 67 .endif 68 // Optional caller-saved registers used by default by the compiler: 69 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select) 70 xchal_sa_align \ptr, 0, 1016, 4, 4 71 rsr \at1, ACCLO // MAC16 option 72 s32i \at1, \ptr, .Lxchal_ofs_+0 73 rsr \at1, ACCHI // MAC16 option 74 s32i \at1, \ptr, .Lxchal_ofs_+4 75 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 76 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 77 xchal_sa_align \ptr, 0, 1016, 4, 4 78 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 79 .endif 80 // Optional caller-saved registers not used by default by the compiler: 81 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 82 xchal_sa_align \ptr, 0, 1004, 4, 4 83 rsr \at1, M0 // MAC16 option 84 s32i \at1, \ptr, .Lxchal_ofs_+0 85 rsr \at1, M1 // MAC16 option 86 s32i \at1, \ptr, .Lxchal_ofs_+4 87 rsr \at1, M2 // MAC16 option 88 s32i \at1, \ptr, .Lxchal_ofs_+8 89 rsr \at1, M3 // MAC16 option 90 s32i \at1, \ptr, .Lxchal_ofs_+12 91 rsr \at1, SCOMPARE1 // conditional store option 92 s32i \at1, \ptr, .Lxchal_ofs_+16 93 .set .Lxchal_ofs_, .Lxchal_ofs_ + 20 94 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 95 xchal_sa_align \ptr, 0, 1004, 4, 4 96 .set .Lxchal_ofs_, .Lxchal_ofs_ + 20 97 .endif 98 .endm // xchal_ncp_store 99 100 /* 101 * Macro to restore all non-coprocessor (extra) custom TIE and optional state 102 * (not including zero-overhead loop registers). 103 * Required parameters: 104 * ptr Save area pointer address register (clobbered) 105 * (register must contain a 4 byte aligned address). 106 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS 107 * registers are clobbered, the remaining are unused). 108 * Optional parameters: 109 * continue If macro invoked as part of a larger load sequence, set to 1 110 * if this is not the first in the sequence. Defaults to 0. 111 * ofs Offset from start of larger sequence (from value of first ptr 112 * in sequence) at which to load. Defaults to next available space 113 * (or 0 if <continue> is 0). 114 * select Select what category(ies) of registers to load, as a bitmask 115 * (see XTHAL_SAS_xxx constants). Defaults to all registers. 116 * alloc Select what category(ies) of registers to allocate; if any 117 * category is selected here that is not in <select>, space for 118 * the corresponding registers is skipped without doing any load. 119 */ 120 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 121 xchal_sa_start \continue, \ofs 122 // Optional global register used by default by the compiler: 123 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) 124 xchal_sa_align \ptr, 0, 1020, 4, 4 125 l32i \at1, \ptr, .Lxchal_ofs_+0 126 wur.THREADPTR \at1 // threadptr option 127 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 128 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 129 xchal_sa_align \ptr, 0, 1020, 4, 4 130 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 131 .endif 132 // Optional caller-saved registers used by default by the compiler: 133 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select) 134 xchal_sa_align \ptr, 0, 1016, 4, 4 135 l32i \at1, \ptr, .Lxchal_ofs_+0 136 wsr \at1, ACCLO // MAC16 option 137 l32i \at1, \ptr, .Lxchal_ofs_+4 138 wsr \at1, ACCHI // MAC16 option 139 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 140 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 141 xchal_sa_align \ptr, 0, 1016, 4, 4 142 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 143 .endif 144 // Optional caller-saved registers not used by default by the compiler: 145 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 146 xchal_sa_align \ptr, 0, 1004, 4, 4 147 l32i \at1, \ptr, .Lxchal_ofs_+0 148 wsr \at1, M0 // MAC16 option 149 l32i \at1, \ptr, .Lxchal_ofs_+4 150 wsr \at1, M1 // MAC16 option 151 l32i \at1, \ptr, .Lxchal_ofs_+8 152 wsr \at1, M2 // MAC16 option 153 l32i \at1, \ptr, .Lxchal_ofs_+12 154 wsr \at1, M3 // MAC16 option 155 l32i \at1, \ptr, .Lxchal_ofs_+16 156 wsr \at1, SCOMPARE1 // conditional store option 157 .set .Lxchal_ofs_, .Lxchal_ofs_ + 20 158 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 159 xchal_sa_align \ptr, 0, 1004, 4, 4 160 .set .Lxchal_ofs_, .Lxchal_ofs_ + 20 161 .endif 162 .endm // xchal_ncp_load 163 164 165 #define XCHAL_NCP_NUM_ATMPS 1 166 167 168 169 #define XCHAL_SA_NUM_ATMPS 1 170 171 #endif /*_XTENSA_CORE_TIE_ASM_H*/ 172 173