1 /* 2 * This header file contains assembly-language definitions (assembly 3 * macros, etc.) for this specific Xtensa processor's TIE extensions 4 * and options. It is customized to this Xtensa processor configuration. 5 * This file is autogenerated, please do not edit. 6 * 7 * Copyright (C) 1999-2010 Tensilica Inc. 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef _XTENSA_CORE_TIE_ASM_H 13 #define _XTENSA_CORE_TIE_ASM_H 14 15 /* Selection parameter values for save-area save/restore macros: */ 16 /* Option vs. TIE: */ 17 #define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ 18 #define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ 19 #define XTHAL_SAS_ANYOT 0x0003 /* both of the above */ 20 /* Whether used automatically by compiler: */ 21 #define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ 22 #define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ 23 #define XTHAL_SAS_ANYCC 0x000C /* both of the above */ 24 /* ABI handling across function calls: */ 25 #define XTHAL_SAS_CALR 0x0010 /* caller-saved */ 26 #define XTHAL_SAS_CALE 0x0020 /* callee-saved */ 27 #define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ 28 #define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */ 29 /* Misc */ 30 #define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ 31 #define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \ 32 | ((ccuse) & XTHAL_SAS_ANYCC) \ 33 | ((abi) & XTHAL_SAS_ANYABI) ) 34 35 36 37 /* 38 * Macro to save all non-coprocessor (extra) custom TIE and optional state 39 * (not including zero-overhead loop registers). 40 * Required parameters: 41 * ptr Save area pointer address register (clobbered) 42 * (register must contain a 4 byte aligned address). 43 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS 44 * registers are clobbered, the remaining are unused). 45 * Optional parameters: 46 * continue If macro invoked as part of a larger store sequence, set to 1 47 * if this is not the first in the sequence. Defaults to 0. 48 * ofs Offset from start of larger sequence (from value of first ptr 49 * in sequence) at which to store. Defaults to next available space 50 * (or 0 if <continue> is 0). 51 * select Select what category(ies) of registers to store, as a bitmask 52 * (see XTHAL_SAS_xxx constants). Defaults to all registers. 53 * alloc Select what category(ies) of registers to allocate; if any 54 * category is selected here that is not in <select>, space for 55 * the corresponding registers is skipped without doing any store. 56 */ 57 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 58 xchal_sa_start \continue, \ofs 59 // Optional global register used by default by the compiler: 60 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) 61 xchal_sa_align \ptr, 0, 1020, 4, 4 62 rur.THREADPTR \at1 // threadptr option 63 s32i \at1, \ptr, .Lxchal_ofs_+0 64 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 65 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 66 xchal_sa_align \ptr, 0, 1020, 4, 4 67 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 68 .endif 69 // Optional caller-saved registers used by default by the compiler: 70 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select) 71 xchal_sa_align \ptr, 0, 1016, 4, 4 72 rsr \at1, ACCLO // MAC16 option 73 s32i \at1, \ptr, .Lxchal_ofs_+0 74 rsr \at1, ACCHI // MAC16 option 75 s32i \at1, \ptr, .Lxchal_ofs_+4 76 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 77 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 78 xchal_sa_align \ptr, 0, 1016, 4, 4 79 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 80 .endif 81 // Optional caller-saved registers not used by default by the compiler: 82 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 83 xchal_sa_align \ptr, 0, 1004, 4, 4 84 rsr \at1, M0 // MAC16 option 85 s32i \at1, \ptr, .Lxchal_ofs_+0 86 rsr \at1, M1 // MAC16 option 87 s32i \at1, \ptr, .Lxchal_ofs_+4 88 rsr \at1, M2 // MAC16 option 89 s32i \at1, \ptr, .Lxchal_ofs_+8 90 rsr \at1, M3 // MAC16 option 91 s32i \at1, \ptr, .Lxchal_ofs_+12 92 rsr \at1, SCOMPARE1 // conditional store option 93 s32i \at1, \ptr, .Lxchal_ofs_+16 94 .set .Lxchal_ofs_, .Lxchal_ofs_ + 20 95 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 96 xchal_sa_align \ptr, 0, 1004, 4, 4 97 .set .Lxchal_ofs_, .Lxchal_ofs_ + 20 98 .endif 99 .endm // xchal_ncp_store 100 101 /* 102 * Macro to restore all non-coprocessor (extra) custom TIE and optional state 103 * (not including zero-overhead loop registers). 104 * Required parameters: 105 * ptr Save area pointer address register (clobbered) 106 * (register must contain a 4 byte aligned address). 107 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS 108 * registers are clobbered, the remaining are unused). 109 * Optional parameters: 110 * continue If macro invoked as part of a larger load sequence, set to 1 111 * if this is not the first in the sequence. Defaults to 0. 112 * ofs Offset from start of larger sequence (from value of first ptr 113 * in sequence) at which to load. Defaults to next available space 114 * (or 0 if <continue> is 0). 115 * select Select what category(ies) of registers to load, as a bitmask 116 * (see XTHAL_SAS_xxx constants). Defaults to all registers. 117 * alloc Select what category(ies) of registers to allocate; if any 118 * category is selected here that is not in <select>, space for 119 * the corresponding registers is skipped without doing any load. 120 */ 121 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 122 xchal_sa_start \continue, \ofs 123 // Optional global register used by default by the compiler: 124 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) 125 xchal_sa_align \ptr, 0, 1020, 4, 4 126 l32i \at1, \ptr, .Lxchal_ofs_+0 127 wur.THREADPTR \at1 // threadptr option 128 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 129 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 130 xchal_sa_align \ptr, 0, 1020, 4, 4 131 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 132 .endif 133 // Optional caller-saved registers used by default by the compiler: 134 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select) 135 xchal_sa_align \ptr, 0, 1016, 4, 4 136 l32i \at1, \ptr, .Lxchal_ofs_+0 137 wsr \at1, ACCLO // MAC16 option 138 l32i \at1, \ptr, .Lxchal_ofs_+4 139 wsr \at1, ACCHI // MAC16 option 140 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 141 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 142 xchal_sa_align \ptr, 0, 1016, 4, 4 143 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 144 .endif 145 // Optional caller-saved registers not used by default by the compiler: 146 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 147 xchal_sa_align \ptr, 0, 1004, 4, 4 148 l32i \at1, \ptr, .Lxchal_ofs_+0 149 wsr \at1, M0 // MAC16 option 150 l32i \at1, \ptr, .Lxchal_ofs_+4 151 wsr \at1, M1 // MAC16 option 152 l32i \at1, \ptr, .Lxchal_ofs_+8 153 wsr \at1, M2 // MAC16 option 154 l32i \at1, \ptr, .Lxchal_ofs_+12 155 wsr \at1, M3 // MAC16 option 156 l32i \at1, \ptr, .Lxchal_ofs_+16 157 wsr \at1, SCOMPARE1 // conditional store option 158 .set .Lxchal_ofs_, .Lxchal_ofs_ + 20 159 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 160 xchal_sa_align \ptr, 0, 1004, 4, 4 161 .set .Lxchal_ofs_, .Lxchal_ofs_ + 20 162 .endif 163 .endm // xchal_ncp_load 164 165 166 #define XCHAL_NCP_NUM_ATMPS 1 167 168 169 170 #define XCHAL_SA_NUM_ATMPS 1 171 172 #endif /*_XTENSA_CORE_TIE_ASM_H*/ 173 174