1 /* 2 * Xtensa processor core configuration information. 3 * This file is autogenerated, please do not edit. 4 * 5 * Copyright (C) 1999-2010 Tensilica Inc. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _XTENSA_CORE_CONFIGURATION_H 11 #define _XTENSA_CORE_CONFIGURATION_H 12 13 14 /**************************************************************************** 15 Parameters Useful for Any Code, USER or PRIVILEGED 16 ****************************************************************************/ 17 18 /* 19 * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is 20 * configured, and a value of 0 otherwise. These macros are always defined. 21 */ 22 23 24 /*---------------------------------------------------------------------- 25 ISA 26 ----------------------------------------------------------------------*/ 27 28 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ 29 #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ 30 #define XCHAL_NUM_AREGS 32 /* num of physical addr regs */ 31 #define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */ 32 #define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */ 33 #define XCHAL_HAVE_DEBUG 1 /* debug option */ 34 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ 35 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ 36 #define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ 37 #define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ 38 #define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ 39 #define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ 40 #define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ 41 #define XCHAL_HAVE_MUL32 1 /* MULL instruction */ 42 #define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */ 43 #define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ 44 #define XCHAL_HAVE_L32R 1 /* L32R instruction */ 45 #define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */ 46 #define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ 47 #define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ 48 #define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ 49 #define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ 50 #define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ 51 #define XCHAL_HAVE_ABS 1 /* ABS instruction */ 52 /*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ 53 /*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ 54 #define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ 55 #define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ 56 #define XCHAL_HAVE_SPECULATION 0 /* speculation */ 57 #define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ 58 #define XCHAL_NUM_CONTEXTS 1 /* */ 59 #define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */ 60 #define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ 61 #define XCHAL_HAVE_PRID 1 /* processor ID register */ 62 #define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ 63 #define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ 64 #define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ 65 #define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ 66 #define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */ 67 #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ 68 #define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */ 69 #define XCHAL_HAVE_MAC16 1 /* MAC16 package */ 70 #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ 71 #define XCHAL_HAVE_FP 0 /* floating point pkg */ 72 #define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ 73 #define XCHAL_HAVE_DFP_accel 0 /* double precision FP acceleration pkg */ 74 #define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ 75 #define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ 76 #define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ 77 #define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ 78 #define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ 79 #define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ 80 #define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ 81 #define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ 82 #define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ 83 #define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ 84 #define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ 85 #define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ 86 #define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ 87 #define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ 88 #define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ 89 90 91 /*---------------------------------------------------------------------- 92 MISC 93 ----------------------------------------------------------------------*/ 94 95 #define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */ 96 #define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */ 97 #define XCHAL_DATA_WIDTH 4 /* data width in bytes */ 98 /* In T1050, applies to selected core load and store instructions (see ISA): */ 99 #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ 100 #define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ 101 #define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */ 102 #define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/ 103 104 #define XCHAL_SW_VERSION 900001 /* sw version of this header */ 105 106 #define XCHAL_CORE_ID "dc233c" /* alphanum core name 107 (CoreID) set in the Xtensa 108 Processor Generator */ 109 110 #define XCHAL_CORE_DESCRIPTION "dc233c" 111 #define XCHAL_BUILD_UNIQUE_ID 0x00004B21 /* 22-bit sw build ID */ 112 113 /* 114 * These definitions describe the hardware targeted by this software. 115 */ 116 #define XCHAL_HW_CONFIGID0 0xC56707FE /* ConfigID hi 32 bits*/ 117 #define XCHAL_HW_CONFIGID1 0x14404B21 /* ConfigID lo 32 bits*/ 118 #define XCHAL_HW_VERSION_NAME "LX4.0.1" /* full version name */ 119 #define XCHAL_HW_VERSION_MAJOR 2400 /* major ver# of targeted hw */ 120 #define XCHAL_HW_VERSION_MINOR 1 /* minor ver# of targeted hw */ 121 #define XCHAL_HW_VERSION 240001 /* major*100+minor */ 122 #define XCHAL_HW_REL_LX4 1 123 #define XCHAL_HW_REL_LX4_0 1 124 #define XCHAL_HW_REL_LX4_0_1 1 125 #define XCHAL_HW_CONFIGID_RELIABLE 1 126 /* If software targets a *range* of hardware versions, these are the bounds: */ 127 #define XCHAL_HW_MIN_VERSION_MAJOR 2400 /* major v of earliest tgt hw */ 128 #define XCHAL_HW_MIN_VERSION_MINOR 1 /* minor v of earliest tgt hw */ 129 #define XCHAL_HW_MIN_VERSION 240001 /* earliest targeted hw */ 130 #define XCHAL_HW_MAX_VERSION_MAJOR 2400 /* major v of latest tgt hw */ 131 #define XCHAL_HW_MAX_VERSION_MINOR 1 /* minor v of latest tgt hw */ 132 #define XCHAL_HW_MAX_VERSION 240001 /* latest targeted hw */ 133 134 135 /*---------------------------------------------------------------------- 136 CACHE 137 ----------------------------------------------------------------------*/ 138 139 #define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */ 140 #define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */ 141 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ 142 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ 143 144 #define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ 145 #define XCHAL_DCACHE_SIZE 16384 /* D-cache size in bytes or 0 */ 146 147 #define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ 148 #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ 149 150 #define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ 151 152 153 154 155 /**************************************************************************** 156 Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code 157 ****************************************************************************/ 158 159 160 #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY 161 162 /*---------------------------------------------------------------------- 163 CACHE 164 ----------------------------------------------------------------------*/ 165 166 #define XCHAL_HAVE_PIF 1 /* any outbound PIF present */ 167 168 /* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ 169 170 /* Number of cache sets in log2(lines per way): */ 171 #define XCHAL_ICACHE_SETWIDTH 7 172 #define XCHAL_DCACHE_SETWIDTH 7 173 174 /* Cache set associativity (number of ways): */ 175 #define XCHAL_ICACHE_WAYS 4 176 #define XCHAL_DCACHE_WAYS 4 177 178 /* Cache features: */ 179 #define XCHAL_ICACHE_LINE_LOCKABLE 1 180 #define XCHAL_DCACHE_LINE_LOCKABLE 1 181 #define XCHAL_ICACHE_ECC_PARITY 0 182 #define XCHAL_DCACHE_ECC_PARITY 0 183 184 /* Cache access size in bytes (affects operation of SICW instruction): */ 185 #define XCHAL_ICACHE_ACCESS_SIZE 4 186 #define XCHAL_DCACHE_ACCESS_SIZE 4 187 188 /* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */ 189 #define XCHAL_CA_BITS 4 190 191 192 /*---------------------------------------------------------------------- 193 INTERNAL I/D RAM/ROMs and XLMI 194 ----------------------------------------------------------------------*/ 195 196 #define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ 197 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */ 198 #define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ 199 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */ 200 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ 201 #define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ 202 203 #define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ 204 205 206 /*---------------------------------------------------------------------- 207 INTERRUPTS and TIMERS 208 ----------------------------------------------------------------------*/ 209 210 #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ 211 #define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ 212 #define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ 213 #define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ 214 #define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ 215 #define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */ 216 #define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ 217 #define XCHAL_NUM_EXTINTERRUPTS 17 /* num of external interrupts */ 218 #define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels 219 (not including level zero) */ 220 #define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ 221 /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ 222 223 /* Masks of interrupts at each interrupt level: */ 224 #define XCHAL_INTLEVEL1_MASK 0x001F80FF 225 #define XCHAL_INTLEVEL2_MASK 0x00000100 226 #define XCHAL_INTLEVEL3_MASK 0x00200E00 227 #define XCHAL_INTLEVEL4_MASK 0x00001000 228 #define XCHAL_INTLEVEL5_MASK 0x00002000 229 #define XCHAL_INTLEVEL6_MASK 0x00000000 230 #define XCHAL_INTLEVEL7_MASK 0x00004000 231 232 /* Masks of interrupts at each range 1..n of interrupt levels: */ 233 #define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x001F80FF 234 #define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x001F81FF 235 #define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x003F8FFF 236 #define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x003F9FFF 237 #define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x003FBFFF 238 #define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x003FBFFF 239 #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF 240 241 /* Level of each interrupt: */ 242 #define XCHAL_INT0_LEVEL 1 243 #define XCHAL_INT1_LEVEL 1 244 #define XCHAL_INT2_LEVEL 1 245 #define XCHAL_INT3_LEVEL 1 246 #define XCHAL_INT4_LEVEL 1 247 #define XCHAL_INT5_LEVEL 1 248 #define XCHAL_INT6_LEVEL 1 249 #define XCHAL_INT7_LEVEL 1 250 #define XCHAL_INT8_LEVEL 2 251 #define XCHAL_INT9_LEVEL 3 252 #define XCHAL_INT10_LEVEL 3 253 #define XCHAL_INT11_LEVEL 3 254 #define XCHAL_INT12_LEVEL 4 255 #define XCHAL_INT13_LEVEL 5 256 #define XCHAL_INT14_LEVEL 7 257 #define XCHAL_INT15_LEVEL 1 258 #define XCHAL_INT16_LEVEL 1 259 #define XCHAL_INT17_LEVEL 1 260 #define XCHAL_INT18_LEVEL 1 261 #define XCHAL_INT19_LEVEL 1 262 #define XCHAL_INT20_LEVEL 1 263 #define XCHAL_INT21_LEVEL 3 264 #define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ 265 #define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ 266 #define XCHAL_NMILEVEL 7 /* NMI "level" (for use with 267 EXCSAVE/EPS/EPC_n, RFI n) */ 268 269 /* Type of each interrupt: */ 270 #define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 271 #define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 272 #define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 273 #define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 274 #define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 275 #define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 276 #define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER 277 #define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE 278 #define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 279 #define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 280 #define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER 281 #define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE 282 #define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 283 #define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER 284 #define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI 285 #define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE 286 #define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE 287 #define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE 288 #define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE 289 #define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE 290 #define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE 291 #define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE 292 293 /* Masks of interrupts for each type of interrupt: */ 294 #define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000 295 #define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880 296 #define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x003F8000 297 #define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F 298 #define XCHAL_INTTYPE_MASK_TIMER 0x00002440 299 #define XCHAL_INTTYPE_MASK_NMI 0x00004000 300 #define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 301 302 /* Interrupt numbers assigned to specific interrupt sources: */ 303 #define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ 304 #define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */ 305 #define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */ 306 #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED 307 #define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */ 308 309 /* Interrupt numbers for levels at which only one interrupt is configured: */ 310 #define XCHAL_INTLEVEL2_NUM 8 311 #define XCHAL_INTLEVEL4_NUM 12 312 #define XCHAL_INTLEVEL5_NUM 13 313 #define XCHAL_INTLEVEL7_NUM 14 314 /* (There are many interrupts each at level(s) 1, 3.) */ 315 316 317 /* 318 * External interrupt vectors/levels. 319 * These macros describe how Xtensa processor interrupt numbers 320 * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) 321 * map to external BInterrupt<n> pins, for those interrupts 322 * configured as external (level-triggered, edge-triggered, or NMI). 323 * See the Xtensa processor databook for more details. 324 */ 325 326 /* Core interrupt numbers mapped to each EXTERNAL interrupt number: */ 327 #define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ 328 #define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ 329 #define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ 330 #define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ 331 #define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ 332 #define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ 333 #define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */ 334 #define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */ 335 #define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */ 336 #define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */ 337 #define XCHAL_EXTINT10_NUM 15 /* (intlevel 1) */ 338 #define XCHAL_EXTINT11_NUM 16 /* (intlevel 1) */ 339 #define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */ 340 #define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */ 341 #define XCHAL_EXTINT14_NUM 19 /* (intlevel 1) */ 342 #define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */ 343 #define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */ 344 345 346 /*---------------------------------------------------------------------- 347 EXCEPTIONS and VECTORS 348 ----------------------------------------------------------------------*/ 349 350 #define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture 351 number: 1 == XEA1 (old) 352 2 == XEA2 (new) 353 0 == XEAX (extern) or TX */ 354 #define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ 355 #define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ 356 #define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ 357 #define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ 358 #define XCHAL_HAVE_HALT 0 /* halt architecture option */ 359 #define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ 360 #define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ 361 #define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ 362 #define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ 363 #define XCHAL_VECBASE_RESET_VADDR 0x00002000 /* VECBASE reset value */ 364 #define XCHAL_VECBASE_RESET_PADDR 0x00002000 365 #define XCHAL_RESET_VECBASE_OVERLAP 0 366 367 #define XCHAL_RESET_VECTOR0_VADDR 0xFE000000 368 #define XCHAL_RESET_VECTOR0_PADDR 0xFE000000 369 #define XCHAL_RESET_VECTOR1_VADDR 0x00001000 370 #define XCHAL_RESET_VECTOR1_PADDR 0x00001000 371 #define XCHAL_RESET_VECTOR_VADDR 0xFE000000 372 #define XCHAL_RESET_VECTOR_PADDR 0xFE000000 373 #define XCHAL_USER_VECOFS 0x00000340 374 #define XCHAL_USER_VECTOR_VADDR 0x00002340 375 #define XCHAL_USER_VECTOR_PADDR 0x00002340 376 #define XCHAL_KERNEL_VECOFS 0x00000300 377 #define XCHAL_KERNEL_VECTOR_VADDR 0x00002300 378 #define XCHAL_KERNEL_VECTOR_PADDR 0x00002300 379 #define XCHAL_DOUBLEEXC_VECOFS 0x000003C0 380 #define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x000023C0 381 #define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x000023C0 382 #define XCHAL_WINDOW_OF4_VECOFS 0x00000000 383 #define XCHAL_WINDOW_UF4_VECOFS 0x00000040 384 #define XCHAL_WINDOW_OF8_VECOFS 0x00000080 385 #define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 386 #define XCHAL_WINDOW_OF12_VECOFS 0x00000100 387 #define XCHAL_WINDOW_UF12_VECOFS 0x00000140 388 #define XCHAL_WINDOW_VECTORS_VADDR 0x00002000 389 #define XCHAL_WINDOW_VECTORS_PADDR 0x00002000 390 #define XCHAL_INTLEVEL2_VECOFS 0x00000180 391 #define XCHAL_INTLEVEL2_VECTOR_VADDR 0x00002180 392 #define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00002180 393 #define XCHAL_INTLEVEL3_VECOFS 0x000001C0 394 #define XCHAL_INTLEVEL3_VECTOR_VADDR 0x000021C0 395 #define XCHAL_INTLEVEL3_VECTOR_PADDR 0x000021C0 396 #define XCHAL_INTLEVEL4_VECOFS 0x00000200 397 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0x00002200 398 #define XCHAL_INTLEVEL4_VECTOR_PADDR 0x00002200 399 #define XCHAL_INTLEVEL5_VECOFS 0x00000240 400 #define XCHAL_INTLEVEL5_VECTOR_VADDR 0x00002240 401 #define XCHAL_INTLEVEL5_VECTOR_PADDR 0x00002240 402 #define XCHAL_INTLEVEL6_VECOFS 0x00000280 403 #define XCHAL_INTLEVEL6_VECTOR_VADDR 0x00002280 404 #define XCHAL_INTLEVEL6_VECTOR_PADDR 0x00002280 405 #define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS 406 #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR 407 #define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR 408 #define XCHAL_NMI_VECOFS 0x000002C0 409 #define XCHAL_NMI_VECTOR_VADDR 0x000022C0 410 #define XCHAL_NMI_VECTOR_PADDR 0x000022C0 411 #define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS 412 #define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR 413 #define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR 414 415 416 /*---------------------------------------------------------------------- 417 DEBUG 418 ----------------------------------------------------------------------*/ 419 420 #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ 421 #define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ 422 #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ 423 #define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */ 424 425 426 /*---------------------------------------------------------------------- 427 MMU 428 ----------------------------------------------------------------------*/ 429 430 /* See core-matmap.h header file for more details. */ 431 432 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ 433 #define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ 434 #define XCHAL_SPANNING_WAY 6 /* TLB spanning way number */ 435 #define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */ 436 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ 437 #define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ 438 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ 439 #define XCHAL_HAVE_PTP_MMU 1 /* full MMU (with page table 440 [autorefill] and protection) 441 usable for an MMU-based OS */ 442 /* If none of the above last 4 are set, it's a custom TLB configuration. */ 443 #define XCHAL_ITLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */ 444 #define XCHAL_DTLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */ 445 446 #define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs */ 447 #define XCHAL_MMU_RINGS 4 /* number of rings (1..4) */ 448 #define XCHAL_MMU_RING_BITS 2 /* num of bits in RING field */ 449 450 #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ 451 452 453 #endif /* _XTENSA_CORE_CONFIGURATION_H */ 454 455