1 /* 2 * This header file describes this specific Xtensa processor's TIE extensions 3 * that extend basic Xtensa core functionality. It is customized to this 4 * Xtensa processor configuration. 5 * This file is autogenerated, please do not edit. 6 * 7 * Copyright (C) 1999-2007 Tensilica Inc. 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef _XTENSA_CORE_TIE_H 13 #define _XTENSA_CORE_TIE_H 14 15 #define XCHAL_CP_NUM 1 /* number of coprocessors */ 16 #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */ 17 #define XCHAL_CP_MASK 0x80 /* bitmask of all CPs by ID */ 18 #define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */ 19 20 /* Basic parameters of each coprocessor: */ 21 #define XCHAL_CP7_NAME "XTIOP" 22 #define XCHAL_CP7_IDENT XTIOP 23 #define XCHAL_CP7_SA_SIZE 0 /* size of state save area */ 24 #define XCHAL_CP7_SA_ALIGN 1 /* min alignment of save area */ 25 #define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */ 26 27 /* Filler info for unassigned coprocessors, to simplify arrays etc: */ 28 #define XCHAL_CP0_SA_SIZE 0 29 #define XCHAL_CP0_SA_ALIGN 1 30 #define XCHAL_CP1_SA_SIZE 0 31 #define XCHAL_CP1_SA_ALIGN 1 32 #define XCHAL_CP2_SA_SIZE 0 33 #define XCHAL_CP2_SA_ALIGN 1 34 #define XCHAL_CP3_SA_SIZE 0 35 #define XCHAL_CP3_SA_ALIGN 1 36 #define XCHAL_CP4_SA_SIZE 0 37 #define XCHAL_CP4_SA_ALIGN 1 38 #define XCHAL_CP5_SA_SIZE 0 39 #define XCHAL_CP5_SA_ALIGN 1 40 #define XCHAL_CP6_SA_SIZE 0 41 #define XCHAL_CP6_SA_ALIGN 1 42 43 /* Save area for non-coprocessor optional and custom (TIE) state: */ 44 #define XCHAL_NCP_SA_SIZE 32 45 #define XCHAL_NCP_SA_ALIGN 4 46 47 /* Total save area for optional and custom state (NCP + CPn): */ 48 #define XCHAL_TOTAL_SA_SIZE 32 /* with 16-byte align padding */ 49 #define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */ 50 51 /* 52 * Detailed contents of save areas. 53 * NOTE: caller must define the XCHAL_SA_REG macro (not defined here) 54 * before expanding the XCHAL_xxx_SA_LIST() macros. 55 * 56 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize, 57 * dbnum,base,regnum,bitsz,gapsz,reset,x...) 58 * 59 * s = passed from XCHAL_*_LIST(s), eg. to select how to expand 60 * ccused = set if used by compiler without special options or code 61 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global) 62 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg) 63 * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg) 64 * name = lowercase reg name (no quotes) 65 * galign = group byte alignment (power of 2) (galign >= align) 66 * align = register byte alignment (power of 2) 67 * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz) 68 * (not including any pad bytes required to galign this or next reg) 69 * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>) 70 * base = reg shortname w/o index (or sr=special, ur=TIE user reg) 71 * regnum = reg index in regfile, or special/TIE-user reg number 72 * bitsz = number of significant bits (regfile width, or ur/sr mask bits) 73 * gapsz = intervening bits, if bitsz bits not stored contiguously 74 * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize) 75 * reset = register reset value (or 0 if undefined at reset) 76 * x = reserved for future use (0 until then) 77 * 78 * To filter out certain registers, e.g. to expand only the non-global 79 * registers used by the compiler, you can do something like this: 80 * 81 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p) 82 * #define SELCC0(p...) 83 * #define SELCC1(abikind,p...) SELAK##abikind(p) 84 * #define SELAK0(p...) REG(p) 85 * #define SELAK1(p...) REG(p) 86 * #define SELAK2(p...) 87 * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \ 88 * ...what you want to expand... 89 */ 90 91 #define XCHAL_NCP_SA_NUM 8 92 #define XCHAL_NCP_SA_LIST(s) \ 93 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \ 94 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \ 95 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \ 96 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \ 97 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \ 98 XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \ 99 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \ 100 XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) 101 102 #define XCHAL_CP0_SA_NUM 0 103 #define XCHAL_CP0_SA_LIST(s) /* empty */ 104 105 #define XCHAL_CP1_SA_NUM 0 106 #define XCHAL_CP1_SA_LIST(s) /* empty */ 107 108 #define XCHAL_CP2_SA_NUM 0 109 #define XCHAL_CP2_SA_LIST(s) /* empty */ 110 111 #define XCHAL_CP3_SA_NUM 0 112 #define XCHAL_CP3_SA_LIST(s) /* empty */ 113 114 #define XCHAL_CP4_SA_NUM 0 115 #define XCHAL_CP4_SA_LIST(s) /* empty */ 116 117 #define XCHAL_CP5_SA_NUM 0 118 #define XCHAL_CP5_SA_LIST(s) /* empty */ 119 120 #define XCHAL_CP6_SA_NUM 0 121 #define XCHAL_CP6_SA_LIST(s) /* empty */ 122 123 #define XCHAL_CP7_SA_NUM 0 124 #define XCHAL_CP7_SA_LIST(s) /* empty */ 125 126 /* Byte length of instruction from its first nibble (op0 field), per FLIX. */ 127 #define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3 128 129 #endif /*_XTENSA_CORE_TIE_H*/ 130 131