1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * This header file describes this specific Xtensa processor's TIE extensions
4  * that extend basic Xtensa core functionality.  It is customized to this
5  * Xtensa processor configuration.
6  * This file is autogenerated, please do not edit.
7  *
8  * Copyright (C) 1999-2007 Tensilica Inc.
9  */
10 
11 #ifndef _XTENSA_CORE_TIE_H
12 #define _XTENSA_CORE_TIE_H
13 
14 #define XCHAL_CP_NUM			1	/* number of coprocessors */
15 #define XCHAL_CP_MAX			8	/* max CP ID + 1 (0 if none) */
16 #define XCHAL_CP_MASK			0x80	/* bitmask of all CPs by ID */
17 #define XCHAL_CP_PORT_MASK		0x80	/* bitmask of only port CPs */
18 
19 /*  Basic parameters of each coprocessor:  */
20 #define XCHAL_CP7_NAME			"XTIOP"
21 #define XCHAL_CP7_IDENT			XTIOP
22 #define XCHAL_CP7_SA_SIZE		0	/* size of state save area */
23 #define XCHAL_CP7_SA_ALIGN		1	/* min alignment of save area */
24 #define XCHAL_CP_ID_XTIOP		7	/* coprocessor ID (0..7) */
25 
26 /*  Filler info for unassigned coprocessors, to simplify arrays etc:  */
27 #define XCHAL_CP0_SA_SIZE		0
28 #define XCHAL_CP0_SA_ALIGN		1
29 #define XCHAL_CP1_SA_SIZE		0
30 #define XCHAL_CP1_SA_ALIGN		1
31 #define XCHAL_CP2_SA_SIZE		0
32 #define XCHAL_CP2_SA_ALIGN		1
33 #define XCHAL_CP3_SA_SIZE		0
34 #define XCHAL_CP3_SA_ALIGN		1
35 #define XCHAL_CP4_SA_SIZE		0
36 #define XCHAL_CP4_SA_ALIGN		1
37 #define XCHAL_CP5_SA_SIZE		0
38 #define XCHAL_CP5_SA_ALIGN		1
39 #define XCHAL_CP6_SA_SIZE		0
40 #define XCHAL_CP6_SA_ALIGN		1
41 
42 /*  Save area for non-coprocessor optional and custom (TIE) state:  */
43 #define XCHAL_NCP_SA_SIZE		32
44 #define XCHAL_NCP_SA_ALIGN		4
45 
46 /*  Total save area for optional and custom state (NCP + CPn):  */
47 #define XCHAL_TOTAL_SA_SIZE		32	/* with 16-byte align padding */
48 #define XCHAL_TOTAL_SA_ALIGN		4	/* actual minimum alignment */
49 
50 /*
51  * Detailed contents of save areas.
52  * NOTE:  caller must define the XCHAL_SA_REG macro (not defined here)
53  * before expanding the XCHAL_xxx_SA_LIST() macros.
54  *
55  * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
56  *		dbnum,base,regnum,bitsz,gapsz,reset,x...)
57  *
58  *	s = passed from XCHAL_*_LIST(s), eg. to select how to expand
59  *	ccused = set if used by compiler without special options or code
60  *	abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
61  *	kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
62  *	opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
63  *	name = lowercase reg name (no quotes)
64  *	galign = group byte alignment (power of 2) (galign >= align)
65  *	align = register byte alignment (power of 2)
66  *	asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
67  *	  (not including any pad bytes required to galign this or next reg)
68  *	dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
69  *	base = reg shortname w/o index (or sr=special, ur=TIE user reg)
70  *	regnum = reg index in regfile, or special/TIE-user reg number
71  *	bitsz = number of significant bits (regfile width, or ur/sr mask bits)
72  *	gapsz = intervening bits, if bitsz bits not stored contiguously
73  *	(padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
74  *	reset = register reset value (or 0 if undefined at reset)
75  *	x = reserved for future use (0 until then)
76  *
77  *  To filter out certain registers, e.g. to expand only the non-global
78  *  registers used by the compiler, you can do something like this:
79  *
80  *  #define XCHAL_SA_REG(s,ccused,p...)	SELCC##ccused(p)
81  *  #define SELCC0(p...)
82  *  #define SELCC1(abikind,p...)	SELAK##abikind(p)
83  *  #define SELAK0(p...)		REG(p)
84  *  #define SELAK1(p...)		REG(p)
85  *  #define SELAK2(p...)
86  *  #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
87  *		...what you want to expand...
88  */
89 
90 #define XCHAL_NCP_SA_NUM	8
91 #define XCHAL_NCP_SA_LIST(s)	\
92  XCHAL_SA_REG(s,1,0,0,1,          acclo, 4, 4, 4,0x0210,  sr,16 , 32,0,0,0) \
93  XCHAL_SA_REG(s,1,0,0,1,          acchi, 4, 4, 4,0x0211,  sr,17 ,  8,0,0,0) \
94  XCHAL_SA_REG(s,0,0,0,1,             m0, 4, 4, 4,0x0220,  sr,32 , 32,0,0,0) \
95  XCHAL_SA_REG(s,0,0,0,1,             m1, 4, 4, 4,0x0221,  sr,33 , 32,0,0,0) \
96  XCHAL_SA_REG(s,0,0,0,1,             m2, 4, 4, 4,0x0222,  sr,34 , 32,0,0,0) \
97  XCHAL_SA_REG(s,0,0,0,1,             m3, 4, 4, 4,0x0223,  sr,35 , 32,0,0,0) \
98  XCHAL_SA_REG(s,0,0,0,1,      scompare1, 4, 4, 4,0x020C,  sr,12 , 32,0,0,0) \
99  XCHAL_SA_REG(s,1,2,1,1,      threadptr, 4, 4, 4,0x03E7,  ur,231, 32,0,0,0)
100 
101 #define XCHAL_CP0_SA_NUM	0
102 #define XCHAL_CP0_SA_LIST(s)	/* empty */
103 
104 #define XCHAL_CP1_SA_NUM	0
105 #define XCHAL_CP1_SA_LIST(s)	/* empty */
106 
107 #define XCHAL_CP2_SA_NUM	0
108 #define XCHAL_CP2_SA_LIST(s)	/* empty */
109 
110 #define XCHAL_CP3_SA_NUM	0
111 #define XCHAL_CP3_SA_LIST(s)	/* empty */
112 
113 #define XCHAL_CP4_SA_NUM	0
114 #define XCHAL_CP4_SA_LIST(s)	/* empty */
115 
116 #define XCHAL_CP5_SA_NUM	0
117 #define XCHAL_CP5_SA_LIST(s)	/* empty */
118 
119 #define XCHAL_CP6_SA_NUM	0
120 #define XCHAL_CP6_SA_LIST(s)	/* empty */
121 
122 #define XCHAL_CP7_SA_NUM	0
123 #define XCHAL_CP7_SA_LIST(s)	/* empty */
124 
125 /* Byte length of instruction from its first nibble (op0 field), per FLIX.  */
126 #define XCHAL_OP0_FORMAT_LENGTHS	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
127 
128 #endif /*_XTENSA_CORE_TIE_H*/
129 
130