1 /* 2 * This header file contains assembly-language definitions (assembly 3 * macros, etc.) for this specific Xtensa processor's TIE extensions 4 * and options. It is customized to this Xtensa processor configuration. 5 * This file is autogenerated, please do not edit. 6 * 7 * Copyright (C) 1999-2007 Tensilica Inc. 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef _XTENSA_CORE_TIE_ASM_H 13 #define _XTENSA_CORE_TIE_ASM_H 14 15 /* Selection parameter values for save-area save/restore macros: */ 16 /* Option vs. TIE: */ 17 #define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ 18 #define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ 19 /* Whether used automatically by compiler: */ 20 #define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ 21 #define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ 22 /* ABI handling across function calls: */ 23 #define XTHAL_SAS_CALR 0x0010 /* caller-saved */ 24 #define XTHAL_SAS_CALE 0x0020 /* callee-saved */ 25 #define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ 26 /* Misc */ 27 #define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ 28 29 30 31 /* Macro to save all non-coprocessor (extra) custom TIE and optional state 32 * (not including zero-overhead loop registers). 33 * Save area ptr (clobbered): ptr (1 byte aligned) 34 * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed) 35 */ 36 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL 37 xchal_sa_start \continue, \ofs 38 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select 39 xchal_sa_align \ptr, 0, 1024-8, 4, 4 40 rsr \at1, ACCLO // MAC16 accumulator 41 rsr \at2, ACCHI 42 s32i \at1, \ptr, .Lxchal_ofs_ + 0 43 s32i \at2, \ptr, .Lxchal_ofs_ + 4 44 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 45 .endif 46 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 47 xchal_sa_align \ptr, 0, 1024-16, 4, 4 48 rsr \at1, M0 // MAC16 registers 49 rsr \at2, M1 50 s32i \at1, \ptr, .Lxchal_ofs_ + 0 51 s32i \at2, \ptr, .Lxchal_ofs_ + 4 52 rsr \at1, M2 53 rsr \at2, M3 54 s32i \at1, \ptr, .Lxchal_ofs_ + 8 55 s32i \at2, \ptr, .Lxchal_ofs_ + 12 56 .set .Lxchal_ofs_, .Lxchal_ofs_ + 16 57 .endif 58 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 59 xchal_sa_align \ptr, 0, 1024-4, 4, 4 60 rsr \at1, SCOMPARE1 // conditional store option 61 s32i \at1, \ptr, .Lxchal_ofs_ + 0 62 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 63 .endif 64 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select 65 xchal_sa_align \ptr, 0, 1024-4, 4, 4 66 rur \at1, THREADPTR // threadptr option 67 s32i \at1, \ptr, .Lxchal_ofs_ + 0 68 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 69 .endif 70 .endm // xchal_ncp_store 71 72 /* Macro to save all non-coprocessor (extra) custom TIE and optional state 73 * (not including zero-overhead loop registers). 74 * Save area ptr (clobbered): ptr (1 byte aligned) 75 * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed) 76 */ 77 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL 78 xchal_sa_start \continue, \ofs 79 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select 80 xchal_sa_align \ptr, 0, 1024-8, 4, 4 81 l32i \at1, \ptr, .Lxchal_ofs_ + 0 82 l32i \at2, \ptr, .Lxchal_ofs_ + 4 83 wsr \at1, ACCLO // MAC16 accumulator 84 wsr \at2, ACCHI 85 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 86 .endif 87 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 88 xchal_sa_align \ptr, 0, 1024-16, 4, 4 89 l32i \at1, \ptr, .Lxchal_ofs_ + 0 90 l32i \at2, \ptr, .Lxchal_ofs_ + 4 91 wsr \at1, M0 // MAC16 registers 92 wsr \at2, M1 93 l32i \at1, \ptr, .Lxchal_ofs_ + 8 94 l32i \at2, \ptr, .Lxchal_ofs_ + 12 95 wsr \at1, M2 96 wsr \at2, M3 97 .set .Lxchal_ofs_, .Lxchal_ofs_ + 16 98 .endif 99 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 100 xchal_sa_align \ptr, 0, 1024-4, 4, 4 101 l32i \at1, \ptr, .Lxchal_ofs_ + 0 102 wsr \at1, SCOMPARE1 // conditional store option 103 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 104 .endif 105 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select 106 xchal_sa_align \ptr, 0, 1024-4, 4, 4 107 l32i \at1, \ptr, .Lxchal_ofs_ + 0 108 wur \at1, THREADPTR // threadptr option 109 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 110 .endif 111 .endm // xchal_ncp_load 112 113 114 115 #define XCHAL_NCP_NUM_ATMPS 2 116 117 118 #define XCHAL_SA_NUM_ATMPS 2 119 120 #endif /*_XTENSA_CORE_TIE_ASM_H*/ 121 122