1*51cb23d4SPatrice Chotard /* 2*51cb23d4SPatrice Chotard * This header provides constants for the reset controller 3*51cb23d4SPatrice Chotard * based peripheral powerdown requests on the STMicroelectronics 4*51cb23d4SPatrice Chotard * STiH407 SoC. 5*51cb23d4SPatrice Chotard */ 6*51cb23d4SPatrice Chotard #ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH407 7*51cb23d4SPatrice Chotard #define _DT_BINDINGS_RESET_CONTROLLER_STIH407 8*51cb23d4SPatrice Chotard 9*51cb23d4SPatrice Chotard /* Powerdown requests control 0 */ 10*51cb23d4SPatrice Chotard #define STIH407_EMISS_POWERDOWN 0 11*51cb23d4SPatrice Chotard #define STIH407_NAND_POWERDOWN 1 12*51cb23d4SPatrice Chotard 13*51cb23d4SPatrice Chotard /* Synp GMAC PowerDown */ 14*51cb23d4SPatrice Chotard #define STIH407_ETH1_POWERDOWN 2 15*51cb23d4SPatrice Chotard 16*51cb23d4SPatrice Chotard /* Powerdown requests control 1 */ 17*51cb23d4SPatrice Chotard #define STIH407_USB3_POWERDOWN 3 18*51cb23d4SPatrice Chotard #define STIH407_USB2_PORT1_POWERDOWN 4 19*51cb23d4SPatrice Chotard #define STIH407_USB2_PORT0_POWERDOWN 5 20*51cb23d4SPatrice Chotard #define STIH407_PCIE1_POWERDOWN 6 21*51cb23d4SPatrice Chotard #define STIH407_PCIE0_POWERDOWN 7 22*51cb23d4SPatrice Chotard #define STIH407_SATA1_POWERDOWN 8 23*51cb23d4SPatrice Chotard #define STIH407_SATA0_POWERDOWN 9 24*51cb23d4SPatrice Chotard 25*51cb23d4SPatrice Chotard /* Reset defines */ 26*51cb23d4SPatrice Chotard #define STIH407_ETH1_SOFTRESET 0 27*51cb23d4SPatrice Chotard #define STIH407_MMC1_SOFTRESET 1 28*51cb23d4SPatrice Chotard #define STIH407_PICOPHY_SOFTRESET 2 29*51cb23d4SPatrice Chotard #define STIH407_IRB_SOFTRESET 3 30*51cb23d4SPatrice Chotard #define STIH407_PCIE0_SOFTRESET 4 31*51cb23d4SPatrice Chotard #define STIH407_PCIE1_SOFTRESET 5 32*51cb23d4SPatrice Chotard #define STIH407_SATA0_SOFTRESET 6 33*51cb23d4SPatrice Chotard #define STIH407_SATA1_SOFTRESET 7 34*51cb23d4SPatrice Chotard #define STIH407_MIPHY0_SOFTRESET 8 35*51cb23d4SPatrice Chotard #define STIH407_MIPHY1_SOFTRESET 9 36*51cb23d4SPatrice Chotard #define STIH407_MIPHY2_SOFTRESET 10 37*51cb23d4SPatrice Chotard #define STIH407_SATA0_PWR_SOFTRESET 11 38*51cb23d4SPatrice Chotard #define STIH407_SATA1_PWR_SOFTRESET 12 39*51cb23d4SPatrice Chotard #define STIH407_DELTA_SOFTRESET 13 40*51cb23d4SPatrice Chotard #define STIH407_BLITTER_SOFTRESET 14 41*51cb23d4SPatrice Chotard #define STIH407_HDTVOUT_SOFTRESET 15 42*51cb23d4SPatrice Chotard #define STIH407_HDQVDP_SOFTRESET 16 43*51cb23d4SPatrice Chotard #define STIH407_VDP_AUX_SOFTRESET 17 44*51cb23d4SPatrice Chotard #define STIH407_COMPO_SOFTRESET 18 45*51cb23d4SPatrice Chotard #define STIH407_HDMI_TX_PHY_SOFTRESET 19 46*51cb23d4SPatrice Chotard #define STIH407_JPEG_DEC_SOFTRESET 20 47*51cb23d4SPatrice Chotard #define STIH407_VP8_DEC_SOFTRESET 21 48*51cb23d4SPatrice Chotard #define STIH407_GPU_SOFTRESET 22 49*51cb23d4SPatrice Chotard #define STIH407_HVA_SOFTRESET 23 50*51cb23d4SPatrice Chotard #define STIH407_ERAM_HVA_SOFTRESET 24 51*51cb23d4SPatrice Chotard #define STIH407_LPM_SOFTRESET 25 52*51cb23d4SPatrice Chotard #define STIH407_KEYSCAN_SOFTRESET 26 53*51cb23d4SPatrice Chotard #define STIH407_USB2_PORT0_SOFTRESET 27 54*51cb23d4SPatrice Chotard #define STIH407_USB2_PORT1_SOFTRESET 28 55*51cb23d4SPatrice Chotard #define STIH407_ST231_AUD_SOFTRESET 29 56*51cb23d4SPatrice Chotard #define STIH407_ST231_DMU_SOFTRESET 30 57*51cb23d4SPatrice Chotard #define STIH407_ST231_GP0_SOFTRESET 31 58*51cb23d4SPatrice Chotard #define STIH407_ST231_GP1_SOFTRESET 32 59*51cb23d4SPatrice Chotard 60*51cb23d4SPatrice Chotard /* Picophy reset defines */ 61*51cb23d4SPatrice Chotard #define STIH407_PICOPHY0_RESET 0 62*51cb23d4SPatrice Chotard #define STIH407_PICOPHY1_RESET 1 63*51cb23d4SPatrice Chotard #define STIH407_PICOPHY2_RESET 2 64*51cb23d4SPatrice Chotard 65*51cb23d4SPatrice Chotard #endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH407 */ 66