183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2c93adc08Smaxims@google.com /* 3c93adc08Smaxims@google.com * Copyright 2017 Google, Inc 4c93adc08Smaxims@google.com */ 5c93adc08Smaxims@google.com 6c93adc08Smaxims@google.com #ifndef _ABI_MACH_ASPEED_AST2500_RESET_H_ 7c93adc08Smaxims@google.com #define _ABI_MACH_ASPEED_AST2500_RESET_H_ 8c93adc08Smaxims@google.com 9c93adc08Smaxims@google.com /* 10c93adc08Smaxims@google.com * The values are intentionally layed out as flags in 11c93adc08Smaxims@google.com * WDT reset parameter. 12c93adc08Smaxims@google.com */ 13*39283ea7Sryan_chen #define ASPEED_RESET_CRT1 (37) 14*39283ea7Sryan_chen #define ASPEED_RESET_RESERVED36 (36) 15*39283ea7Sryan_chen #define ASPEED_RESET_RESERVED35 (35) 16*39283ea7Sryan_chen #define ASPEED_RESET_RESERVED34 (34) 17*39283ea7Sryan_chen #define ASPEED_RESET_RESERVED33 (33) 18*39283ea7Sryan_chen #define ASPEED_RESET_RESERVED32 (32) 19c93adc08Smaxims@google.com 20*39283ea7Sryan_chen #define ASPEED_RESET_RESERVED31 (31) 21*39283ea7Sryan_chen #define ASPEED_RESET_RESERVED30 (30) 22*39283ea7Sryan_chen #define ASPEED_RESET_RESERVED29 (29) 23*39283ea7Sryan_chen #define ASPEED_RESET_RESERVED28 (28) 24*39283ea7Sryan_chen #define ASPEED_RESET_RESERVED27 (27) 25*39283ea7Sryan_chen #define ASPEED_RESET_RESERVED26 (26) 26*39283ea7Sryan_chen #define ASPEED_RESET_XDMA (25) 27*39283ea7Sryan_chen #define ASPEED_RESET_MCTP (24) 28*39283ea7Sryan_chen #define ASPEED_RESET_ADC (23) 29*39283ea7Sryan_chen #define ASPEED_RESET_JTAG_MASTER (22) 30*39283ea7Sryan_chen #define ASPEED_RESET_RESERVED21 (21) 31*39283ea7Sryan_chen #define ASPEED_RESET_RESERVED20 (20) 32*39283ea7Sryan_chen #define ASPEED_RESET_RESERVED19 (19) 33*39283ea7Sryan_chen #define ASPEED_RESET_MIC (18) 34*39283ea7Sryan_chen #define ASPEED_RESET_RESERVED17 (17) 35*39283ea7Sryan_chen #define ASEPPD_RESET_SDIO (16) 36*39283ea7Sryan_chen #define ASPEED_RESET_UHCI (15) 37*39283ea7Sryan_chen #define ASPEED_RESET_EHCI_P1 (14) 38*39283ea7Sryan_chen #define ASPEED_RESET_CRT (13) 39*39283ea7Sryan_chen #define ASPEED_RESET_MAC2 (12) 40*39283ea7Sryan_chen #define ASPEED_RESET_MAC1 (11) 41*39283ea7Sryan_chen #define ASPEED_RESET_PECI (10) 42*39283ea7Sryan_chen #define ASPEED_RESET_PWM (9) 43*39283ea7Sryan_chen #define ASPEED_RESET_PCI_VGA (8) 44*39283ea7Sryan_chen #define ASPEED_RESET_2D (7) 45*39283ea7Sryan_chen #define ASPEED_RESET_VIDEO (6) 46*39283ea7Sryan_chen #define ASPEED_RESET_LPC_ESPI (5) 47*39283ea7Sryan_chen #define ASPEED_RESET_HACE (4) 48*39283ea7Sryan_chen #define ASPEED_RESET_EHCI_P2 (3) 49*39283ea7Sryan_chen #define ASPEED_RESET_I2C (2) 50*39283ea7Sryan_chen #define ASPEED_RESET_AHB (1) 51*39283ea7Sryan_chen #define ASPEED_RESET_SDRAM (0) 52c93adc08Smaxims@google.com 53c93adc08Smaxims@google.com #endif /* _ABI_MACH_ASPEED_AST2500_RESET_H_ */ 54