1 /* 2 * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de> 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H 15 #define _DT_BINDINGS_RESET_ALTR_RST_MGR_H 16 17 /* MPUMODRST */ 18 #define CPU0_RESET 0 19 #define CPU1_RESET 1 20 #define WDS_RESET 2 21 #define SCUPER_RESET 3 22 #define L2_RESET 4 23 24 /* PERMODRST */ 25 #define EMAC0_RESET 32 26 #define EMAC1_RESET 33 27 #define USB0_RESET 34 28 #define USB1_RESET 35 29 #define NAND_RESET 36 30 #define QSPI_RESET 37 31 #define L4WD0_RESET 38 32 #define L4WD1_RESET 39 33 #define OSC1TIMER0_RESET 40 34 #define OSC1TIMER1_RESET 41 35 #define SPTIMER0_RESET 42 36 #define SPTIMER1_RESET 43 37 #define I2C0_RESET 44 38 #define I2C1_RESET 45 39 #define I2C2_RESET 46 40 #define I2C3_RESET 47 41 #define UART0_RESET 48 42 #define UART1_RESET 49 43 #define SPIM0_RESET 50 44 #define SPIM1_RESET 51 45 #define SPIS0_RESET 52 46 #define SPIS1_RESET 53 47 #define SDMMC_RESET 54 48 #define CAN0_RESET 55 49 #define CAN1_RESET 56 50 #define GPIO0_RESET 57 51 #define GPIO1_RESET 58 52 #define GPIO2_RESET 59 53 #define DMA_RESET 60 54 #define SDR_RESET 61 55 56 /* PER2MODRST */ 57 #define DMAIF0_RESET 64 58 #define DMAIF1_RESET 65 59 #define DMAIF2_RESET 66 60 #define DMAIF3_RESET 67 61 #define DMAIF4_RESET 68 62 #define DMAIF5_RESET 69 63 #define DMAIF6_RESET 70 64 #define DMAIF7_RESET 71 65 66 /* BRGMODRST */ 67 #define HPS2FPGA_RESET 96 68 #define LWHPS2FPGA_RESET 97 69 #define FPGA2HPS_RESET 98 70 71 /* MISCMODRST*/ 72 #define ROM_RESET 128 73 #define OCRAM_RESET 129 74 #define SYSMGR_RESET 130 75 #define SYSMGRCOLD_RESET 131 76 #define FPGAMGR_RESET 132 77 #define ACPIDMAP_RESET 133 78 #define S2F_RESET 134 79 #define S2FCOLD_RESET 135 80 #define NRSTPIN_RESET 136 81 #define TIMESTAMPCOLD_RESET 137 82 #define CLKMGRCOLD_RESET 138 83 #define SCANMGR_RESET 139 84 #define FRZCTRLCOLD_RESET 140 85 #define SYSDBG_RESET 141 86 #define DBG_RESET 142 87 #define TAPCOLD_RESET 143 88 #define SDRCOLD_RESET 144 89 90 #endif 91