1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 4 */ 5 6 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H 7 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H 8 9 /* core clocks */ 10 #define PLL_APLL 1 11 #define PLL_DPLL 2 12 #define PLL_GPLL 3 13 #define ARMCLK 4 14 15 /* sclk gates (special clocks) */ 16 #define SCLK_GPU 64 17 #define SCLK_SPI 65 18 #define SCLK_SDMMC 68 19 #define SCLK_SDIO 69 20 #define SCLK_EMMC 71 21 #define SCLK_NANDC 76 22 #define SCLK_UART0 77 23 #define SCLK_UART1 78 24 #define SCLK_UART2 79 25 #define SCLK_I2S 82 26 #define SCLK_SPDIF 83 27 #define SCLK_TIMER0 85 28 #define SCLK_TIMER1 86 29 #define SCLK_TIMER2 87 30 #define SCLK_TIMER3 88 31 #define SCLK_SARADC 91 32 #define SCLK_OTGPHY0 93 33 #define SCLK_LCDC 100 34 #define SCLK_HDMI 109 35 #define SCLK_HEVC 111 36 #define SCLK_I2S_OUT 113 37 #define SCLK_SDMMC_DRV 114 38 #define SCLK_SDIO_DRV 115 39 #define SCLK_EMMC_DRV 117 40 #define SCLK_SDMMC_SAMPLE 118 41 #define SCLK_SDIO_SAMPLE 119 42 #define SCLK_EMMC_SAMPLE 121 43 #define SCLK_PVTM_CORE 123 44 #define SCLK_PVTM_GPU 124 45 #define SCLK_PVTM_VIDEO 125 46 #define SCLK_MAC 151 47 #define SCLK_MACREF 152 48 #define SCLK_SFC 160 49 50 #define DCLK_LCDC 190 51 52 /* aclk gates */ 53 #define ACLK_DMAC2 194 54 #define ACLK_VIO0 197 55 #define ACLK_VIO1 203 56 #define ACLK_VCODEC 208 57 #define ACLK_CPU 209 58 #define ACLK_PERI 210 59 60 /* pclk gates */ 61 #define PCLK_SARADC 318 62 #define PCLK_GPIO0 320 63 #define PCLK_GPIO1 321 64 #define PCLK_GPIO2 322 65 #define PCLK_GPIO3 323 66 #define PCLK_GRF 329 67 #define PCLK_I2C0 332 68 #define PCLK_I2C1 333 69 #define PCLK_I2C2 334 70 #define PCLK_I2C3 335 71 #define PCLK_SPI 338 72 #define PCLK_UART0 341 73 #define PCLK_UART1 342 74 #define PCLK_UART2 343 75 #define PCLK_PWM 350 76 #define PCLK_TIMER 353 77 #define PCLK_HDMI 360 78 #define PCLK_CPU 362 79 #define PCLK_PERI 363 80 #define PCLK_DDRUPCTL 364 81 #define PCLK_WDT 368 82 83 /* hclk gates */ 84 #define HCLK_OTG0 449 85 #define HCLK_OTG1 450 86 #define HCLK_NANDC 453 87 #define HCLK_SDMMC 456 88 #define HCLK_SDIO 457 89 #define HCLK_EMMC 459 90 #define HCLK_I2S 462 91 #define HCLK_LCDC 465 92 #define HCLK_ROM 467 93 #define HCLK_VIO_BUS 472 94 #define HCLK_VCODEC 476 95 #define HCLK_CPU 477 96 #define HCLK_PERI 478 97 98 #define CLK_NR_CLKS (HCLK_PERI + 1) 99 100 /* soft-reset indices */ 101 #define SRST_CORE0 0 102 #define SRST_CORE1 1 103 #define SRST_CORE0_DBG 4 104 #define SRST_CORE1_DBG 5 105 #define SRST_CORE0_POR 8 106 #define SRST_CORE1_POR 9 107 #define SRST_L2C 12 108 #define SRST_TOPDBG 13 109 #define SRST_STRC_SYS_A 14 110 #define SRST_PD_CORE_NIU 15 111 112 #define SRST_TIMER2 16 113 #define SRST_CPUSYS_H 17 114 #define SRST_AHB2APB_H 19 115 #define SRST_TIMER3 20 116 #define SRST_INTMEM 21 117 #define SRST_ROM 22 118 #define SRST_PERI_NIU 23 119 #define SRST_I2S 24 120 #define SRST_DDR_PLL 25 121 #define SRST_GPU_DLL 26 122 #define SRST_TIMER0 27 123 #define SRST_TIMER1 28 124 #define SRST_CORE_DLL 29 125 #define SRST_EFUSE_P 30 126 #define SRST_ACODEC_P 31 127 128 #define SRST_GPIO0 32 129 #define SRST_GPIO1 33 130 #define SRST_GPIO2 34 131 #define SRST_UART0 39 132 #define SRST_UART1 40 133 #define SRST_UART2 41 134 #define SRST_I2C0 43 135 #define SRST_I2C1 44 136 #define SRST_I2C2 45 137 #define SRST_SFC 47 138 139 #define SRST_PWM0 48 140 #define SRST_DAP 51 141 #define SRST_DAP_SYS 52 142 #define SRST_GRF 55 143 #define SRST_PERIPHSYS_A 57 144 #define SRST_PERIPHSYS_H 58 145 #define SRST_PERIPHSYS_P 59 146 #define SRST_CPU_PERI 61 147 #define SRST_EMEM_PERI 62 148 #define SRST_USB_PERI 63 149 150 #define SRST_DMA2 64 151 #define SRST_MAC 66 152 #define SRST_NANDC 68 153 #define SRST_USBOTG0 69 154 #define SRST_OTGC0 71 155 #define SRST_USBOTG1 72 156 #define SRST_OTGC1 74 157 #define SRST_DDRMSCH 79 158 159 #define SRST_MMC0 81 160 #define SRST_SDIO 82 161 #define SRST_EMMC 83 162 #define SRST_SPI0 84 163 #define SRST_WDT 86 164 #define SRST_SARADC 87 165 #define SRST_DDRPHY 88 166 #define SRST_DDRPHY_P 89 167 #define SRST_DDRCTRL 90 168 #define SRST_DDRCTRL_P 91 169 170 #define SRST_HDMI_P 96 171 #define SRST_VIO_BUS_H 99 172 #define SRST_UTMI0 103 173 #define SRST_UTMI1 104 174 #define SRST_USBPOR 105 175 176 #define SRST_VCODEC_A 112 177 #define SRST_VCODEC_H 113 178 #define SRST_VIO1_A 114 179 #define SRST_HEVC 115 180 #define SRST_VCODEC_NIU_A 116 181 #define SRST_LCDC1_A 117 182 #define SRST_LCDC1_H 118 183 #define SRST_LCDC1_D 119 184 #define SRST_GPU 120 185 #define SRST_GPU_NIU_A 122 186 187 #define SRST_DBG_P 131 188 189 #endif 190