1*07d538d2SMario Six /* SPDX-License-Identifier: GPL-2.0+ */ 2*07d538d2SMario Six /* 3*07d538d2SMario Six * (C) Copyright 2018 4*07d538d2SMario Six * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc 5*07d538d2SMario Six */ 6*07d538d2SMario Six 7*07d538d2SMario Six #ifndef DT_BINDINGS_MPC83XX_CLK_H 8*07d538d2SMario Six #define DT_BINDINGS_MPC83XX_CLK_H 9*07d538d2SMario Six #define MPC83XX_CLK_CORE 0 10*07d538d2SMario Six #define MPC83XX_CLK_CSB 1 11*07d538d2SMario Six #define MPC83XX_CLK_QE 2 12*07d538d2SMario Six #define MPC83XX_CLK_BRG 3 13*07d538d2SMario Six #define MPC83XX_CLK_LBIU 4 14*07d538d2SMario Six #define MPC83XX_CLK_LCLK 5 15*07d538d2SMario Six #define MPC83XX_CLK_MEM 6 16*07d538d2SMario Six #define MPC83XX_CLK_MEM_SEC 7 17*07d538d2SMario Six #define MPC83XX_CLK_ENC 8 18*07d538d2SMario Six #define MPC83XX_CLK_I2C1 9 19*07d538d2SMario Six #define MPC83XX_CLK_I2C2 10 20*07d538d2SMario Six #define MPC83XX_CLK_TDM 11 21*07d538d2SMario Six #define MPC83XX_CLK_SDHC 12 22*07d538d2SMario Six #define MPC83XX_CLK_TSEC1 13 23*07d538d2SMario Six #define MPC83XX_CLK_TSEC2 14 24*07d538d2SMario Six #define MPC83XX_CLK_USBDR 15 25*07d538d2SMario Six #define MPC83XX_CLK_USBMPH 16 26*07d538d2SMario Six #define MPC83XX_CLK_PCIEXP1 17 27*07d538d2SMario Six #define MPC83XX_CLK_PCIEXP2 18 28*07d538d2SMario Six #define MPC83XX_CLK_SATA 19 29*07d538d2SMario Six #define MPC83XX_CLK_DMAC 20 30*07d538d2SMario Six #define MPC83XX_CLK_PCI 21 31*07d538d2SMario Six /* Count */ 32*07d538d2SMario Six #define MPC83XX_CLK_COUNT 22 33*07d538d2SMario Six #endif /* DT_BINDINGS_MPC83XX_CLK_H */ 34