1d47ab0ecSGraeme Russ /* 2d47ab0ecSGraeme Russ * (C) Copyright 2011 3d47ab0ecSGraeme Russ * Graeme Russ, <graeme.russ@gmail.com> 4d47ab0ecSGraeme Russ * 51a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 6d47ab0ecSGraeme Russ */ 7c17ca6b5SBin Meng 8d47ab0ecSGraeme Russ #include <common.h> 9*1221ce45SMasahiro Yamada #include <linux/errno.h> 10db55bd7dSSimon Glass #include <asm/mtrr.h> 11d47ab0ecSGraeme Russ 12d47ab0ecSGraeme Russ DECLARE_GLOBAL_DATA_PTR; 13d47ab0ecSGraeme Russ 145e98947fSSimon Glass /* Get the top of usable RAM */ 155e98947fSSimon Glass __weak ulong board_get_usable_ram_top(ulong total_size) 16a1d57b7aSGraeme Russ { 175e98947fSSimon Glass return gd->ram_size; 185e98947fSSimon Glass } 195e98947fSSimon Glass 20a1d57b7aSGraeme Russ int init_cache_f_r(void) 21a1d57b7aSGraeme Russ { 22db55bd7dSSimon Glass #if defined(CONFIG_X86_RESET_VECTOR) & !defined(CONFIG_HAVE_FSP) 23db55bd7dSSimon Glass int ret; 24db55bd7dSSimon Glass 25db55bd7dSSimon Glass ret = mtrr_commit(false); 263b621ccaSBin Meng /* If MTRR MSR is not implemented by the processor, just ignore it */ 273b621ccaSBin Meng if (ret && ret != -ENOSYS) 28db55bd7dSSimon Glass return ret; 29db55bd7dSSimon Glass #endif 30a1d57b7aSGraeme Russ /* Initialise the CPU cache(s) */ 31a1d57b7aSGraeme Russ return init_cache(); 32a1d57b7aSGraeme Russ } 33a1d57b7aSGraeme Russ 34d47ab0ecSGraeme Russ bd_t bd_data; 35d47ab0ecSGraeme Russ 36d47ab0ecSGraeme Russ int init_bd_struct_r(void) 37d47ab0ecSGraeme Russ { 38d47ab0ecSGraeme Russ gd->bd = &bd_data; 39d47ab0ecSGraeme Russ memset(gd->bd, 0, sizeof(bd_t)); 40d47ab0ecSGraeme Russ 41d47ab0ecSGraeme Russ return 0; 42d47ab0ecSGraeme Russ } 43