1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2d47ab0ecSGraeme Russ /* 3d47ab0ecSGraeme Russ * (C) Copyright 2011 4d47ab0ecSGraeme Russ * Graeme Russ, <graeme.russ@gmail.com> 5d47ab0ecSGraeme Russ */ 6c17ca6b5SBin Meng 7d47ab0ecSGraeme Russ #include <common.h> 81221ce45SMasahiro Yamada #include <linux/errno.h> 9db55bd7dSSimon Glass #include <asm/mtrr.h> 10d47ab0ecSGraeme Russ 11d47ab0ecSGraeme Russ DECLARE_GLOBAL_DATA_PTR; 12d47ab0ecSGraeme Russ 135e98947fSSimon Glass /* Get the top of usable RAM */ board_get_usable_ram_top(ulong total_size)145e98947fSSimon Glass__weak ulong board_get_usable_ram_top(ulong total_size) 15a1d57b7aSGraeme Russ { 165e98947fSSimon Glass return gd->ram_size; 175e98947fSSimon Glass } 185e98947fSSimon Glass init_cache_f_r(void)19a1d57b7aSGraeme Russint init_cache_f_r(void) 20a1d57b7aSGraeme Russ { 212eff9895SSimon Glass #if CONFIG_IS_ENABLED(X86_32BIT_INIT) && !defined(CONFIG_HAVE_FSP) 22db55bd7dSSimon Glass int ret; 23db55bd7dSSimon Glass 24db55bd7dSSimon Glass ret = mtrr_commit(false); 253b621ccaSBin Meng /* If MTRR MSR is not implemented by the processor, just ignore it */ 263b621ccaSBin Meng if (ret && ret != -ENOSYS) 27db55bd7dSSimon Glass return ret; 28db55bd7dSSimon Glass #endif 29a1d57b7aSGraeme Russ /* Initialise the CPU cache(s) */ 30a1d57b7aSGraeme Russ return init_cache(); 31a1d57b7aSGraeme Russ } 32