1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> 4 */ 5 6 #include <common.h> 7 #include <dm.h> 8 #include <vbe.h> 9 #include <video.h> 10 #include <asm/fsp/fsp_support.h> 11 12 DECLARE_GLOBAL_DATA_PTR; 13 14 struct pixel { 15 u8 pos; 16 u8 size; 17 }; 18 19 static const struct fsp_framebuffer { 20 struct pixel red; 21 struct pixel green; 22 struct pixel blue; 23 struct pixel rsvd; 24 } fsp_framebuffer_format_map[] = { 25 [pixel_rgbx_8bpc] = { {0, 8}, {8, 8}, {16, 8}, {24, 8} }, 26 [pixel_bgrx_8bpc] = { {16, 8}, {8, 8}, {0, 8}, {24, 8} }, 27 }; 28 29 static int save_vesa_mode(struct vesa_mode_info *vesa) 30 { 31 const struct hob_graphics_info *ginfo; 32 const struct fsp_framebuffer *fbinfo; 33 34 ginfo = fsp_get_graphics_info(gd->arch.hob_list, NULL); 35 36 /* 37 * If there is no graphics info structure, bail out and keep 38 * running on the serial console. 39 * 40 * Note: on some platforms (eg: Braswell), the FSP will not produce 41 * the graphics info HOB unless you plug some cables to the display 42 * interface (eg: HDMI) on the board. 43 */ 44 if (!ginfo) { 45 debug("FSP graphics hand-off block not found\n"); 46 return -ENXIO; 47 } 48 49 vesa->x_resolution = ginfo->width; 50 vesa->y_resolution = ginfo->height; 51 vesa->bits_per_pixel = 32; 52 vesa->bytes_per_scanline = ginfo->pixels_per_scanline * 4; 53 vesa->phys_base_ptr = ginfo->fb_base; 54 55 if (ginfo->pixel_format >= pixel_bitmask) { 56 debug("FSP set unknown framebuffer format: %d\n", 57 ginfo->pixel_format); 58 return -EINVAL; 59 } 60 fbinfo = &fsp_framebuffer_format_map[ginfo->pixel_format]; 61 vesa->red_mask_size = fbinfo->red.size; 62 vesa->red_mask_pos = fbinfo->red.pos; 63 vesa->green_mask_size = fbinfo->green.size; 64 vesa->green_mask_pos = fbinfo->green.pos; 65 vesa->blue_mask_size = fbinfo->blue.size; 66 vesa->blue_mask_pos = fbinfo->blue.pos; 67 vesa->reserved_mask_size = fbinfo->rsvd.size; 68 vesa->reserved_mask_pos = fbinfo->rsvd.pos; 69 70 return 0; 71 } 72 73 static int fsp_video_probe(struct udevice *dev) 74 { 75 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); 76 struct video_priv *uc_priv = dev_get_uclass_priv(dev); 77 struct vesa_mode_info *vesa = &mode_info.vesa; 78 int ret; 79 80 printf("Video: "); 81 82 /* Initialize vesa_mode_info structure */ 83 ret = save_vesa_mode(vesa); 84 if (ret) 85 goto err; 86 87 /* 88 * The framebuffer base address in the FSP graphics info HOB reflects 89 * the value assigned by the FSP. After PCI enumeration the framebuffer 90 * base address may be relocated. Let's get the updated one from device. 91 * 92 * For IGD, it seems to be always on BAR2. 93 */ 94 vesa->phys_base_ptr = dm_pci_read_bar32(dev, 2); 95 96 ret = vbe_setup_video_priv(vesa, uc_priv, plat); 97 if (ret) 98 goto err; 99 100 printf("%dx%dx%d\n", uc_priv->xsize, uc_priv->ysize, 101 vesa->bits_per_pixel); 102 103 return 0; 104 105 err: 106 printf("No video mode configured in FSP!\n"); 107 return ret; 108 } 109 110 static const struct udevice_id fsp_video_ids[] = { 111 { .compatible = "fsp-fb" }, 112 { } 113 }; 114 115 U_BOOT_DRIVER(fsp_video) = { 116 .name = "fsp_video", 117 .id = UCLASS_VIDEO, 118 .of_match = fsp_video_ids, 119 .probe = fsp_video_probe, 120 }; 121 122 static struct pci_device_id fsp_video_supported[] = { 123 { PCI_DEVICE_CLASS(PCI_CLASS_DISPLAY_VGA << 8, 0xffff00) }, 124 { }, 125 }; 126 127 U_BOOT_PCI_DEVICE(fsp_video, fsp_video_supported); 128