1 /* 2 * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <vbe.h> 10 #include <video.h> 11 #include <asm/fsp/fsp_support.h> 12 13 DECLARE_GLOBAL_DATA_PTR; 14 15 struct pixel { 16 u8 pos; 17 u8 size; 18 }; 19 20 static const struct fsp_framebuffer { 21 struct pixel red; 22 struct pixel green; 23 struct pixel blue; 24 struct pixel rsvd; 25 } fsp_framebuffer_format_map[] = { 26 [pixel_rgbx_8bpc] = { {0, 8}, {8, 8}, {16, 8}, {24, 8} }, 27 [pixel_bgrx_8bpc] = { {16, 8}, {8, 8}, {0, 8}, {24, 8} }, 28 }; 29 30 static int save_vesa_mode(struct vesa_mode_info *vesa) 31 { 32 const struct hob_graphics_info *ginfo; 33 const struct fsp_framebuffer *fbinfo; 34 35 ginfo = fsp_get_graphics_info(gd->arch.hob_list, NULL); 36 37 /* 38 * If there is no graphics info structure, bail out and keep 39 * running on the serial console. 40 * 41 * Note: on some platforms (eg: Braswell), the FSP will not produce 42 * the graphics info HOB unless you plug some cables to the display 43 * interface (eg: HDMI) on the board. 44 */ 45 if (!ginfo) { 46 debug("FSP graphics hand-off block not found\n"); 47 return -ENXIO; 48 } 49 50 vesa->x_resolution = ginfo->width; 51 vesa->y_resolution = ginfo->height; 52 vesa->bits_per_pixel = 32; 53 vesa->bytes_per_scanline = ginfo->pixels_per_scanline * 4; 54 vesa->phys_base_ptr = ginfo->fb_base; 55 56 if (ginfo->pixel_format >= pixel_bitmask) { 57 debug("FSP set unknown framebuffer format: %d\n", 58 ginfo->pixel_format); 59 return -EINVAL; 60 } 61 fbinfo = &fsp_framebuffer_format_map[ginfo->pixel_format]; 62 vesa->red_mask_size = fbinfo->red.size; 63 vesa->red_mask_pos = fbinfo->red.pos; 64 vesa->green_mask_size = fbinfo->green.size; 65 vesa->green_mask_pos = fbinfo->green.pos; 66 vesa->blue_mask_size = fbinfo->blue.size; 67 vesa->blue_mask_pos = fbinfo->blue.pos; 68 vesa->reserved_mask_size = fbinfo->rsvd.size; 69 vesa->reserved_mask_pos = fbinfo->rsvd.pos; 70 71 return 0; 72 } 73 74 static int fsp_video_probe(struct udevice *dev) 75 { 76 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); 77 struct video_priv *uc_priv = dev_get_uclass_priv(dev); 78 struct vesa_mode_info *vesa = &mode_info.vesa; 79 int ret; 80 81 printf("Video: "); 82 83 /* Initialize vesa_mode_info structure */ 84 ret = save_vesa_mode(vesa); 85 if (ret) 86 goto err; 87 88 /* 89 * The framebuffer base address in the FSP graphics info HOB reflects 90 * the value assigned by the FSP. After PCI enumeration the framebuffer 91 * base address may be relocated. Let's get the updated one from device. 92 * 93 * For IGD, it seems to be always on BAR2. 94 */ 95 vesa->phys_base_ptr = dm_pci_read_bar32(dev, 2); 96 97 ret = vbe_setup_video_priv(vesa, uc_priv, plat); 98 if (ret) 99 goto err; 100 101 printf("%dx%dx%d\n", uc_priv->xsize, uc_priv->ysize, 102 vesa->bits_per_pixel); 103 104 return 0; 105 106 err: 107 printf("No video mode configured in FSP!\n"); 108 return ret; 109 } 110 111 static const struct udevice_id fsp_video_ids[] = { 112 { .compatible = "fsp-fb" }, 113 { } 114 }; 115 116 U_BOOT_DRIVER(fsp_video) = { 117 .name = "fsp_video", 118 .id = UCLASS_VIDEO, 119 .of_match = fsp_video_ids, 120 .probe = fsp_video_probe, 121 }; 122 123 static struct pci_device_id fsp_video_supported[] = { 124 { PCI_DEVICE_CLASS(PCI_CLASS_DISPLAY_VGA << 8, 0xffff00) }, 125 { }, 126 }; 127 128 U_BOOT_PCI_DEVICE(fsp_video, fsp_video_supported); 129