xref: /openbmc/u-boot/arch/x86/lib/fsp/fsp_dram.c (revision f1056910)
1 /*
2  * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <asm/fsp/fsp_support.h>
9 #include <asm/e820.h>
10 #include <asm/mrccache.h>
11 #include <asm/post.h>
12 
13 DECLARE_GLOBAL_DATA_PTR;
14 
15 int dram_init(void)
16 {
17 	phys_size_t ram_size = 0;
18 	const struct hob_header *hdr;
19 	struct hob_res_desc *res_desc;
20 
21 	hdr = gd->arch.hob_list;
22 	while (!end_of_hob(hdr)) {
23 		if (hdr->type == HOB_TYPE_RES_DESC) {
24 			res_desc = (struct hob_res_desc *)hdr;
25 			if (res_desc->type == RES_SYS_MEM ||
26 			    res_desc->type == RES_MEM_RESERVED) {
27 				ram_size += res_desc->len;
28 			}
29 		}
30 		hdr = get_next_hob(hdr);
31 	}
32 
33 	gd->ram_size = ram_size;
34 	post_code(POST_DRAM);
35 
36 #ifdef CONFIG_ENABLE_MRC_CACHE
37 	gd->arch.mrc_output = fsp_get_nvs_data(gd->arch.hob_list,
38 					       &gd->arch.mrc_output_len);
39 #endif
40 
41 	return 0;
42 }
43 
44 void dram_init_banksize(void)
45 {
46 	gd->bd->bi_dram[0].start = 0;
47 	gd->bd->bi_dram[0].size = gd->ram_size;
48 }
49 
50 /*
51  * This function looks for the highest region of memory lower than 4GB which
52  * has enough space for U-Boot where U-Boot is aligned on a page boundary.
53  * It overrides the default implementation found elsewhere which simply
54  * picks the end of ram, wherever that may be. The location of the stack,
55  * the relocation address, and how far U-Boot is moved by relocation are
56  * set in the global data structure.
57  */
58 ulong board_get_usable_ram_top(ulong total_size)
59 {
60 	return fsp_get_usable_lowmem_top(gd->arch.hob_list);
61 }
62 
63 unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
64 {
65 	unsigned num_entries = 0;
66 	const struct hob_header *hdr;
67 	struct hob_res_desc *res_desc;
68 
69 	hdr = gd->arch.hob_list;
70 
71 	while (!end_of_hob(hdr)) {
72 		if (hdr->type == HOB_TYPE_RES_DESC) {
73 			res_desc = (struct hob_res_desc *)hdr;
74 			entries[num_entries].addr = res_desc->phys_start;
75 			entries[num_entries].size = res_desc->len;
76 
77 			if (res_desc->type == RES_SYS_MEM)
78 				entries[num_entries].type = E820_RAM;
79 			else if (res_desc->type == RES_MEM_RESERVED)
80 				entries[num_entries].type = E820_RESERVED;
81 
82 			num_entries++;
83 		}
84 		hdr = get_next_hob(hdr);
85 	}
86 
87 	/* Mark PCIe ECAM address range as reserved */
88 	entries[num_entries].addr = CONFIG_PCIE_ECAM_BASE;
89 	entries[num_entries].size = CONFIG_PCIE_ECAM_SIZE;
90 	entries[num_entries].type = E820_RESERVED;
91 	num_entries++;
92 
93 	return num_entries;
94 }
95