1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 4 */ 5 6 #include <common.h> 7 #include <asm/fsp/fsp_support.h> 8 #include <asm/e820.h> 9 #include <asm/mrccache.h> 10 #include <asm/post.h> 11 12 DECLARE_GLOBAL_DATA_PTR; 13 dram_init(void)14int dram_init(void) 15 { 16 phys_size_t ram_size = 0; 17 const struct hob_header *hdr; 18 struct hob_res_desc *res_desc; 19 20 hdr = gd->arch.hob_list; 21 while (!end_of_hob(hdr)) { 22 if (hdr->type == HOB_TYPE_RES_DESC) { 23 res_desc = (struct hob_res_desc *)hdr; 24 if (res_desc->type == RES_SYS_MEM || 25 res_desc->type == RES_MEM_RESERVED) { 26 ram_size += res_desc->len; 27 } 28 } 29 hdr = get_next_hob(hdr); 30 } 31 32 gd->ram_size = ram_size; 33 post_code(POST_DRAM); 34 35 #ifdef CONFIG_ENABLE_MRC_CACHE 36 gd->arch.mrc_output = fsp_get_nvs_data(gd->arch.hob_list, 37 &gd->arch.mrc_output_len); 38 #endif 39 40 return 0; 41 } 42 dram_init_banksize(void)43int dram_init_banksize(void) 44 { 45 gd->bd->bi_dram[0].start = 0; 46 gd->bd->bi_dram[0].size = gd->ram_size; 47 48 return 0; 49 } 50 51 /* 52 * This function looks for the highest region of memory lower than 4GB which 53 * has enough space for U-Boot where U-Boot is aligned on a page boundary. 54 * It overrides the default implementation found elsewhere which simply 55 * picks the end of ram, wherever that may be. The location of the stack, 56 * the relocation address, and how far U-Boot is moved by relocation are 57 * set in the global data structure. 58 */ board_get_usable_ram_top(ulong total_size)59ulong board_get_usable_ram_top(ulong total_size) 60 { 61 return fsp_get_usable_lowmem_top(gd->arch.hob_list); 62 } 63 install_e820_map(unsigned int max_entries,struct e820_entry * entries)64unsigned int install_e820_map(unsigned int max_entries, 65 struct e820_entry *entries) 66 { 67 unsigned int num_entries = 0; 68 const struct hob_header *hdr; 69 struct hob_res_desc *res_desc; 70 71 hdr = gd->arch.hob_list; 72 73 while (!end_of_hob(hdr)) { 74 if (hdr->type == HOB_TYPE_RES_DESC) { 75 res_desc = (struct hob_res_desc *)hdr; 76 entries[num_entries].addr = res_desc->phys_start; 77 entries[num_entries].size = res_desc->len; 78 79 if (res_desc->type == RES_SYS_MEM) 80 entries[num_entries].type = E820_RAM; 81 else if (res_desc->type == RES_MEM_RESERVED) 82 entries[num_entries].type = E820_RESERVED; 83 84 num_entries++; 85 } 86 hdr = get_next_hob(hdr); 87 } 88 89 /* Mark PCIe ECAM address range as reserved */ 90 entries[num_entries].addr = CONFIG_PCIE_ECAM_BASE; 91 entries[num_entries].size = CONFIG_PCIE_ECAM_SIZE; 92 entries[num_entries].type = E820_RESERVED; 93 num_entries++; 94 95 #ifdef CONFIG_HAVE_ACPI_RESUME 96 /* 97 * Everything between U-Boot's stack and ram top needs to be 98 * reserved in order for ACPI S3 resume to work. 99 */ 100 entries[num_entries].addr = gd->start_addr_sp - CONFIG_STACK_SIZE; 101 entries[num_entries].size = gd->ram_top - gd->start_addr_sp + \ 102 CONFIG_STACK_SIZE; 103 entries[num_entries].type = E820_RESERVED; 104 num_entries++; 105 #endif 106 107 return num_entries; 108 } 109