1 /* 2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <errno.h> 10 #include <rtc.h> 11 #include <asm/acpi_s3.h> 12 #include <asm/cmos_layout.h> 13 #include <asm/early_cmos.h> 14 #include <asm/io.h> 15 #include <asm/mrccache.h> 16 #include <asm/post.h> 17 #include <asm/processor.h> 18 #include <asm/fsp/fsp_support.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 extern void ich_spi_config_opcode(struct udevice *dev); 23 24 int checkcpu(void) 25 { 26 return 0; 27 } 28 29 int print_cpuinfo(void) 30 { 31 post_code(POST_CPU_INFO); 32 return default_print_cpuinfo(); 33 } 34 35 int fsp_init_phase_pci(void) 36 { 37 u32 status; 38 39 /* call into FspNotify */ 40 debug("Calling into FSP (notify phase INIT_PHASE_PCI): "); 41 status = fsp_notify(NULL, INIT_PHASE_PCI); 42 if (status) 43 debug("fail, error code %x\n", status); 44 else 45 debug("OK\n"); 46 47 return status ? -EPERM : 0; 48 } 49 50 void board_final_cleanup(void) 51 { 52 u32 status; 53 54 #ifdef CONFIG_FSP_LOCKDOWN_SPI 55 struct udevice *dev; 56 57 /* 58 * Some Intel FSP (like Braswell) does SPI lock-down during the call 59 * to fsp_notify(INIT_PHASE_BOOT). But before SPI lock-down is done, 60 * it's bootloader's responsibility to configure the SPI controller's 61 * opcode registers properly otherwise SPI controller driver doesn't 62 * know how to communicate with the SPI flash device. 63 * 64 * Note we cannot do such configuration elsewhere (eg: during the SPI 65 * controller driver's probe() routine), because: 66 * 67 * 1). U-Boot SPI controller driver does not set the lock-down bit 68 * 2). Any SPI transfer will corrupt the contents of these registers 69 * 70 * Hence we have to do it right here before SPI lock-down bit is set. 71 */ 72 if (!uclass_first_device_err(UCLASS_SPI, &dev)) 73 ich_spi_config_opcode(dev); 74 #endif 75 76 /* call into FspNotify */ 77 debug("Calling into FSP (notify phase INIT_PHASE_BOOT): "); 78 status = fsp_notify(NULL, INIT_PHASE_BOOT); 79 if (status) 80 debug("fail, error code %x\n", status); 81 else 82 debug("OK\n"); 83 84 return; 85 } 86 87 static __maybe_unused void *fsp_prepare_mrc_cache(void) 88 { 89 struct mrc_data_container *cache; 90 struct mrc_region entry; 91 int ret; 92 93 ret = mrccache_get_region(NULL, &entry); 94 if (ret) 95 return NULL; 96 97 cache = mrccache_find_current(&entry); 98 if (!cache) 99 return NULL; 100 101 debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__, 102 cache->data, cache->data_size, cache->checksum); 103 104 return cache->data; 105 } 106 107 #ifdef CONFIG_HAVE_ACPI_RESUME 108 int fsp_save_s3_stack(void) 109 { 110 struct udevice *dev; 111 int ret; 112 113 if (gd->arch.prev_sleep_state == ACPI_S3) 114 return 0; 115 116 ret = uclass_get_device(UCLASS_RTC, 0, &dev); 117 if (ret) { 118 debug("Cannot find RTC: err=%d\n", ret); 119 return -ENODEV; 120 } 121 122 /* Save the stack address to CMOS */ 123 ret = rtc_write32(dev, CMOS_FSP_STACK_ADDR, gd->start_addr_sp); 124 if (ret) { 125 debug("Save stack address to CMOS: err=%d\n", ret); 126 return -EIO; 127 } 128 129 return 0; 130 } 131 #endif 132 133 int arch_fsp_init(void) 134 { 135 void *nvs; 136 int stack = CONFIG_FSP_TEMP_RAM_ADDR; 137 int boot_mode = BOOT_FULL_CONFIG; 138 #ifdef CONFIG_HAVE_ACPI_RESUME 139 int prev_sleep_state = chipset_prev_sleep_state(); 140 gd->arch.prev_sleep_state = prev_sleep_state; 141 #endif 142 143 if (!gd->arch.hob_list) { 144 #ifdef CONFIG_ENABLE_MRC_CACHE 145 nvs = fsp_prepare_mrc_cache(); 146 #else 147 nvs = NULL; 148 #endif 149 150 #ifdef CONFIG_HAVE_ACPI_RESUME 151 if (prev_sleep_state == ACPI_S3) { 152 if (nvs == NULL) { 153 /* If waking from S3 and no cache then */ 154 debug("No MRC cache found in S3 resume path\n"); 155 post_code(POST_RESUME_FAILURE); 156 /* Clear Sleep Type */ 157 chipset_clear_sleep_state(); 158 /* Reboot */ 159 debug("Rebooting..\n"); 160 reset_cpu(0); 161 /* Should not reach here.. */ 162 panic("Reboot System"); 163 } 164 165 /* 166 * DM is not avaiable yet at this point, hence call 167 * CMOS access library which does not depend on DM. 168 */ 169 stack = cmos_read32(CMOS_FSP_STACK_ADDR); 170 boot_mode = BOOT_ON_S3_RESUME; 171 } 172 #endif 173 /* 174 * The first time we enter here, call fsp_init(). 175 * Note the execution does not return to this function, 176 * instead it jumps to fsp_continue(). 177 */ 178 fsp_init(stack, boot_mode, nvs); 179 } else { 180 /* 181 * The second time we enter here, adjust the size of malloc() 182 * pool before relocation. Given gd->malloc_base was adjusted 183 * after the call to board_init_f_init_reserve() in arch/x86/ 184 * cpu/start.S, we should fix up gd->malloc_limit here. 185 */ 186 gd->malloc_limit += CONFIG_FSP_SYS_MALLOC_F_LEN; 187 } 188 189 return 0; 190 } 191