1 /* 2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <errno.h> 10 #include <rtc.h> 11 #include <asm/acpi_s3.h> 12 #include <asm/cmos_layout.h> 13 #include <asm/early_cmos.h> 14 #include <asm/io.h> 15 #include <asm/mrccache.h> 16 #include <asm/post.h> 17 #include <asm/processor.h> 18 #include <asm/fsp/fsp_support.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 int checkcpu(void) 23 { 24 return 0; 25 } 26 27 int print_cpuinfo(void) 28 { 29 post_code(POST_CPU_INFO); 30 return default_print_cpuinfo(); 31 } 32 33 int fsp_init_phase_pci(void) 34 { 35 u32 status; 36 37 /* call into FspNotify */ 38 debug("Calling into FSP (notify phase INIT_PHASE_PCI): "); 39 status = fsp_notify(NULL, INIT_PHASE_PCI); 40 if (status) 41 debug("fail, error code %x\n", status); 42 else 43 debug("OK\n"); 44 45 return status ? -EPERM : 0; 46 } 47 48 void board_final_cleanup(void) 49 { 50 u32 status; 51 52 /* call into FspNotify */ 53 debug("Calling into FSP (notify phase INIT_PHASE_BOOT): "); 54 status = fsp_notify(NULL, INIT_PHASE_BOOT); 55 if (status) 56 debug("fail, error code %x\n", status); 57 else 58 debug("OK\n"); 59 60 return; 61 } 62 63 static __maybe_unused void *fsp_prepare_mrc_cache(void) 64 { 65 struct mrc_data_container *cache; 66 struct mrc_region entry; 67 int ret; 68 69 ret = mrccache_get_region(NULL, &entry); 70 if (ret) 71 return NULL; 72 73 cache = mrccache_find_current(&entry); 74 if (!cache) 75 return NULL; 76 77 debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__, 78 cache->data, cache->data_size, cache->checksum); 79 80 return cache->data; 81 } 82 83 #ifdef CONFIG_HAVE_ACPI_RESUME 84 int fsp_save_s3_stack(void) 85 { 86 struct udevice *dev; 87 int ret; 88 89 if (gd->arch.prev_sleep_state == ACPI_S3) 90 return 0; 91 92 ret = uclass_get_device(UCLASS_RTC, 0, &dev); 93 if (ret) { 94 debug("Cannot find RTC: err=%d\n", ret); 95 return -ENODEV; 96 } 97 98 /* Save the stack address to CMOS */ 99 ret = rtc_write32(dev, CMOS_FSP_STACK_ADDR, gd->start_addr_sp); 100 if (ret) { 101 debug("Save stack address to CMOS: err=%d\n", ret); 102 return -EIO; 103 } 104 105 return 0; 106 } 107 #endif 108 109 int arch_fsp_init(void) 110 { 111 void *nvs; 112 int stack = CONFIG_FSP_TEMP_RAM_ADDR; 113 int boot_mode = BOOT_FULL_CONFIG; 114 #ifdef CONFIG_HAVE_ACPI_RESUME 115 int prev_sleep_state = chipset_prev_sleep_state(); 116 gd->arch.prev_sleep_state = prev_sleep_state; 117 #endif 118 119 if (!gd->arch.hob_list) { 120 #ifdef CONFIG_ENABLE_MRC_CACHE 121 nvs = fsp_prepare_mrc_cache(); 122 #else 123 nvs = NULL; 124 #endif 125 126 #ifdef CONFIG_HAVE_ACPI_RESUME 127 if (prev_sleep_state == ACPI_S3) { 128 if (nvs == NULL) { 129 /* If waking from S3 and no cache then */ 130 debug("No MRC cache found in S3 resume path\n"); 131 post_code(POST_RESUME_FAILURE); 132 /* Clear Sleep Type */ 133 chipset_clear_sleep_state(); 134 /* Reboot */ 135 debug("Rebooting..\n"); 136 reset_cpu(0); 137 /* Should not reach here.. */ 138 panic("Reboot System"); 139 } 140 141 /* 142 * DM is not avaiable yet at this point, hence call 143 * CMOS access library which does not depend on DM. 144 */ 145 stack = cmos_read32(CMOS_FSP_STACK_ADDR); 146 boot_mode = BOOT_ON_S3_RESUME; 147 } 148 #endif 149 /* 150 * The first time we enter here, call fsp_init(). 151 * Note the execution does not return to this function, 152 * instead it jumps to fsp_continue(). 153 */ 154 fsp_init(stack, boot_mode, nvs); 155 } else { 156 /* 157 * The second time we enter here, adjust the size of malloc() 158 * pool before relocation. Given gd->malloc_base was adjusted 159 * after the call to board_init_f_init_reserve() in arch/x86/ 160 * cpu/start.S, we should fix up gd->malloc_limit here. 161 */ 162 gd->malloc_limit += CONFIG_FSP_SYS_MALLOC_F_LEN; 163 } 164 165 return 0; 166 } 167