1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> 4 */ 5 6 #include <common.h> 7 #include <vbe.h> 8 #include <asm/acpi_s3.h> 9 #include <asm/coreboot_tables.h> 10 #include <asm/e820.h> 11 12 DECLARE_GLOBAL_DATA_PTR; 13 14 int high_table_reserve(void) 15 { 16 /* adjust stack pointer to reserve space for configuration tables */ 17 gd->arch.high_table_limit = gd->start_addr_sp; 18 gd->start_addr_sp -= CONFIG_HIGH_TABLE_SIZE; 19 gd->arch.high_table_ptr = gd->start_addr_sp; 20 21 /* clear the memory */ 22 #ifdef CONFIG_HAVE_ACPI_RESUME 23 if (gd->arch.prev_sleep_state != ACPI_S3) 24 #endif 25 memset((void *)gd->arch.high_table_ptr, 0, 26 CONFIG_HIGH_TABLE_SIZE); 27 28 gd->start_addr_sp &= ~0xf; 29 30 return 0; 31 } 32 33 void *high_table_malloc(size_t bytes) 34 { 35 u32 new_ptr; 36 void *ptr; 37 38 new_ptr = gd->arch.high_table_ptr + bytes; 39 if (new_ptr >= gd->arch.high_table_limit) 40 return NULL; 41 ptr = (void *)gd->arch.high_table_ptr; 42 gd->arch.high_table_ptr = new_ptr; 43 44 return ptr; 45 } 46 47 /** 48 * cb_table_init() - initialize a coreboot table header 49 * 50 * This fills in the coreboot table header signature and the header bytes. 51 * Other fields are set to zero. 52 * 53 * @cbh: coreboot table header address 54 */ 55 static void cb_table_init(struct cb_header *cbh) 56 { 57 memset(cbh, 0, sizeof(struct cb_header)); 58 memcpy(cbh->signature, "LBIO", 4); 59 cbh->header_bytes = sizeof(struct cb_header); 60 } 61 62 /** 63 * cb_table_add_entry() - add a coreboot table entry 64 * 65 * This increases the coreboot table entry size with added table entry length 66 * and increases entry count by 1. 67 * 68 * @cbh: coreboot table header address 69 * @cbr: to be added table entry address 70 * @return: pointer to next table entry address 71 */ 72 static u32 cb_table_add_entry(struct cb_header *cbh, struct cb_record *cbr) 73 { 74 cbh->table_bytes += cbr->size; 75 cbh->table_entries++; 76 77 return (u32)cbr + cbr->size; 78 } 79 80 /** 81 * cb_table_finalize() - finalize the coreboot table 82 * 83 * This calculates the checksum for all coreboot table entries as well as 84 * the checksum for the coreboot header itself. 85 * 86 * @cbh: coreboot table header address 87 */ 88 static void cb_table_finalize(struct cb_header *cbh) 89 { 90 struct cb_record *cbr = (struct cb_record *)(cbh + 1); 91 92 cbh->table_checksum = compute_ip_checksum(cbr, cbh->table_bytes); 93 cbh->header_checksum = compute_ip_checksum(cbh, cbh->header_bytes); 94 } 95 96 void write_coreboot_table(u32 addr, struct memory_area *cfg_tables) 97 { 98 struct cb_header *cbh = (struct cb_header *)addr; 99 struct cb_record *cbr; 100 struct cb_memory *mem; 101 struct cb_memory_range *map; 102 struct e820_entry e820[32]; 103 struct cb_framebuffer *fb; 104 struct vesa_mode_info *vesa; 105 int i, num; 106 107 cb_table_init(cbh); 108 cbr = (struct cb_record *)(cbh + 1); 109 110 /* 111 * Two type of coreboot table entries are generated by us. 112 * They are 'struct cb_memory' and 'struct cb_framebuffer'. 113 */ 114 115 /* populate memory map table */ 116 mem = (struct cb_memory *)cbr; 117 mem->tag = CB_TAG_MEMORY; 118 map = mem->map; 119 120 /* first install e820 defined memory maps */ 121 num = install_e820_map(ARRAY_SIZE(e820), e820); 122 for (i = 0; i < num; i++) { 123 map->start.lo = e820[i].addr & 0xffffffff; 124 map->start.hi = e820[i].addr >> 32; 125 map->size.lo = e820[i].size & 0xffffffff; 126 map->size.hi = e820[i].size >> 32; 127 map->type = e820[i].type; 128 map++; 129 } 130 131 /* then install all configuration tables */ 132 while (cfg_tables->size) { 133 map->start.lo = cfg_tables->start & 0xffffffff; 134 map->start.hi = cfg_tables->start >> 32; 135 map->size.lo = cfg_tables->size & 0xffffffff; 136 map->size.hi = cfg_tables->size >> 32; 137 map->type = CB_MEM_TABLE; 138 map++; 139 num++; 140 cfg_tables++; 141 } 142 mem->size = num * sizeof(struct cb_memory_range) + 143 sizeof(struct cb_record); 144 cbr = (struct cb_record *)cb_table_add_entry(cbh, cbr); 145 146 /* populate framebuffer table if we have sane vesa info */ 147 vesa = &mode_info.vesa; 148 if (vesa->x_resolution && vesa->y_resolution) { 149 fb = (struct cb_framebuffer *)cbr; 150 fb->tag = CB_TAG_FRAMEBUFFER; 151 fb->size = sizeof(struct cb_framebuffer); 152 153 fb->x_resolution = vesa->x_resolution; 154 fb->y_resolution = vesa->y_resolution; 155 fb->bits_per_pixel = vesa->bits_per_pixel; 156 fb->bytes_per_line = vesa->bytes_per_scanline; 157 fb->physical_address = vesa->phys_base_ptr; 158 fb->red_mask_size = vesa->red_mask_size; 159 fb->red_mask_pos = vesa->red_mask_pos; 160 fb->green_mask_size = vesa->green_mask_size; 161 fb->green_mask_pos = vesa->green_mask_pos; 162 fb->blue_mask_size = vesa->blue_mask_size; 163 fb->blue_mask_pos = vesa->blue_mask_pos; 164 fb->reserved_mask_size = vesa->reserved_mask_size; 165 fb->reserved_mask_pos = vesa->reserved_mask_pos; 166 167 cbr = (struct cb_record *)cb_table_add_entry(cbh, cbr); 168 } 169 170 cb_table_finalize(cbh); 171 } 172