1*5e2400e8SBin Meng /* 2*5e2400e8SBin Meng * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 3*5e2400e8SBin Meng * 4*5e2400e8SBin Meng * SPDX-License-Identifier: GPL-2.0+ 5*5e2400e8SBin Meng */ 6*5e2400e8SBin Meng 7*5e2400e8SBin Meng #ifndef _X86_TABLES_H_ 8*5e2400e8SBin Meng #define _X86_TABLES_H_ 9*5e2400e8SBin Meng 10*5e2400e8SBin Meng /* 11*5e2400e8SBin Meng * All x86 tables happen to like the address range from 0xf0000 to 0x100000. 12*5e2400e8SBin Meng * We use 0xf0000 as the starting address to store those tables, including 13*5e2400e8SBin Meng * PIRQ routing table, Multi-Processor table and ACPI table. 14*5e2400e8SBin Meng */ 15*5e2400e8SBin Meng #define ROM_TABLE_ADDR 0xf0000 16*5e2400e8SBin Meng 17*5e2400e8SBin Meng /** 18*5e2400e8SBin Meng * table_compute_checksum() - Compute a table checksum 19*5e2400e8SBin Meng * 20*5e2400e8SBin Meng * This computes an 8-bit checksum for the configuration table. 21*5e2400e8SBin Meng * All bytes in the configuration table, including checksum itself and 22*5e2400e8SBin Meng * reserved bytes must add up to zero. 23*5e2400e8SBin Meng * 24*5e2400e8SBin Meng * @v: configuration table base address 25*5e2400e8SBin Meng * @len: configuration table size 26*5e2400e8SBin Meng * @return: the 8-bit checksum 27*5e2400e8SBin Meng */ 28*5e2400e8SBin Meng u8 table_compute_checksum(void *v, int len); 29*5e2400e8SBin Meng 30*5e2400e8SBin Meng /** 31*5e2400e8SBin Meng * write_tables() - Write x86 configuration tables 32*5e2400e8SBin Meng * 33*5e2400e8SBin Meng * This writes x86 configuration tables, including PIRQ routing table, 34*5e2400e8SBin Meng * Multi-Processor table and ACPI table. Whether a specific type of 35*5e2400e8SBin Meng * configuration table is written is controlled by a Kconfig option. 36*5e2400e8SBin Meng */ 37*5e2400e8SBin Meng void write_tables(void); 38*5e2400e8SBin Meng 39*5e2400e8SBin Meng /** 40*5e2400e8SBin Meng * write_pirq_routing_table() - Write PIRQ routing table 41*5e2400e8SBin Meng * 42*5e2400e8SBin Meng * This writes PIRQ routing table at a given address. 43*5e2400e8SBin Meng * 44*5e2400e8SBin Meng * @start: start address to write PIRQ routing table 45*5e2400e8SBin Meng * @return: end address of PIRQ routing table 46*5e2400e8SBin Meng */ 47*5e2400e8SBin Meng u32 write_pirq_routing_table(u32 start); 48*5e2400e8SBin Meng 49*5e2400e8SBin Meng #endif /* _X86_TABLES_H_ */ 50