1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2bb416465SFelipe Balbi /* 3bb416465SFelipe Balbi * Copyright (c) 2017 Intel Corporation 4bb416465SFelipe Balbi */ 5bb416465SFelipe Balbi #ifndef _X86_ASM_SCU_IPC_H_ 6bb416465SFelipe Balbi #define _X86_ASM_SCU_IPC_H_ 7bb416465SFelipe Balbi 8bb416465SFelipe Balbi /* IPC defines the following message types */ 9bb416465SFelipe Balbi #define IPCMSG_WARM_RESET 0xf0 10bb416465SFelipe Balbi #define IPCMSG_COLD_RESET 0xf1 11bb416465SFelipe Balbi #define IPCMSG_SOFT_RESET 0xf2 12bb416465SFelipe Balbi #define IPCMSG_COLD_BOOT 0xf3 13bb416465SFelipe Balbi #define IPCMSG_GET_FW_REVISION 0xf4 14bb416465SFelipe Balbi #define IPCMSG_WATCHDOG_TIMER 0xf8 /* Set Kernel Watchdog Threshold */ 15bb416465SFelipe Balbi 16bb416465SFelipe Balbi struct ipc_ifwi_version { 17bb416465SFelipe Balbi u16 minor; 18bb416465SFelipe Balbi u8 major; 19bb416465SFelipe Balbi u8 hardware_id; 20bb416465SFelipe Balbi u32 reserved[3]; 21bb416465SFelipe Balbi }; 22bb416465SFelipe Balbi 23bb416465SFelipe Balbi /* Issue commands to the SCU with or without data */ 24bb416465SFelipe Balbi int scu_ipc_simple_command(u32 cmd, u32 sub); 25bb416465SFelipe Balbi int scu_ipc_command(u32 cmd, u32 sub, u32 *in, int inlen, u32 *out, int outlen); 26bb416465SFelipe Balbi 27bb416465SFelipe Balbi #endif /* _X86_ASM_SCU_IPC_H_ */ 28