1fea25720SGraeme Russ /* 2fea25720SGraeme Russ * (C) Copyright 2002 3fa82f871SAlbert ARIBAUD * Daniel Engström, Omicron Ceti AB, daniel@omicron.se 4fea25720SGraeme Russ * 51a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 6fea25720SGraeme Russ */ 7fea25720SGraeme Russ 8fea25720SGraeme Russ #ifndef __ASM_PROCESSOR_H_ 9fea25720SGraeme Russ #define __ASM_PROCESSOR_H_ 1 10fea25720SGraeme Russ 11109ad143SGraeme Russ #define X86_GDT_ENTRY_SIZE 8 12109ad143SGraeme Russ 13e34aef1dSSimon Glass #define X86_GDT_ENTRY_NULL 0 14e34aef1dSSimon Glass #define X86_GDT_ENTRY_UNUSED 1 15e34aef1dSSimon Glass #define X86_GDT_ENTRY_32BIT_CS 2 16109ad143SGraeme Russ #define X86_GDT_ENTRY_32BIT_DS 3 17e34aef1dSSimon Glass #define X86_GDT_ENTRY_32BIT_FS 4 18e34aef1dSSimon Glass #define X86_GDT_ENTRY_16BIT_CS 5 19e34aef1dSSimon Glass #define X86_GDT_ENTRY_16BIT_DS 6 20e34aef1dSSimon Glass #define X86_GDT_ENTRY_16BIT_FLAT_CS 7 21e34aef1dSSimon Glass #define X86_GDT_ENTRY_16BIT_FLAT_DS 8 22e34aef1dSSimon Glass #define X86_GDT_NUM_ENTRIES 9 23109ad143SGraeme Russ 24109ad143SGraeme Russ #define X86_GDT_SIZE (X86_GDT_NUM_ENTRIES * X86_GDT_ENTRY_SIZE) 25fea25720SGraeme Russ 26*45b5a378SSimon Glass /* Length of the public header on Intel microcode blobs */ 27*45b5a378SSimon Glass #define UCODE_HEADER_LEN 0x30 28*45b5a378SSimon Glass 2921b9b14bSSimon Glass #ifndef __ASSEMBLY__ 3021b9b14bSSimon Glass 31ff6a8f3cSSimon Glass /* 32ff6a8f3cSSimon Glass * This register is documented in (for example) the Intel Atom Processor E3800 33ff6a8f3cSSimon Glass * Product Family Datasheet in "PCU - Power Management Controller (PMC)". 34ff6a8f3cSSimon Glass * 35ff6a8f3cSSimon Glass * RST_CNT: Reset Control Register (RST_CNT) Offset cf9. 36ff6a8f3cSSimon Glass * 37ff6a8f3cSSimon Glass * The naming follows Intel's naming. 38ff6a8f3cSSimon Glass */ 39f5fbbe95SSimon Glass #define PORT_RESET 0xcf9 40f5fbbe95SSimon Glass 41ff6a8f3cSSimon Glass enum { 42ff6a8f3cSSimon Glass SYS_RST = 1 << 1, /* 0 for soft reset, 1 for hard reset */ 43ff6a8f3cSSimon Glass RST_CPU = 1 << 2, /* initiate reset */ 44ff6a8f3cSSimon Glass FULL_RST = 1 << 3, /* full power cycle */ 45ff6a8f3cSSimon Glass }; 46ff6a8f3cSSimon Glass 47ff6a8f3cSSimon Glass /** 48ff6a8f3cSSimon Glass * x86_full_reset() - reset everything: perform a full power cycle 49ff6a8f3cSSimon Glass */ 50ff6a8f3cSSimon Glass void x86_full_reset(void); 51ff6a8f3cSSimon Glass 5221b9b14bSSimon Glass static inline __attribute__((always_inline)) void cpu_hlt(void) 5321b9b14bSSimon Glass { 5421b9b14bSSimon Glass asm("hlt"); 5521b9b14bSSimon Glass } 5621b9b14bSSimon Glass 5721b9b14bSSimon Glass static inline ulong cpu_get_sp(void) 5821b9b14bSSimon Glass { 5921b9b14bSSimon Glass ulong result; 6021b9b14bSSimon Glass 6121b9b14bSSimon Glass asm volatile( 6221b9b14bSSimon Glass "mov %%esp, %%eax" 6321b9b14bSSimon Glass : "=a" (result)); 6421b9b14bSSimon Glass return result; 6521b9b14bSSimon Glass } 6621b9b14bSSimon Glass 6721b9b14bSSimon Glass #endif /* __ASSEMBLY__ */ 6821b9b14bSSimon Glass 69fea25720SGraeme Russ #endif 70