1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2fea25720SGraeme Russ /* 3fea25720SGraeme Russ * (C) Copyright 2002 4fa82f871SAlbert ARIBAUD * Daniel Engström, Omicron Ceti AB, daniel@omicron.se 5fea25720SGraeme Russ */ 6fea25720SGraeme Russ 7fea25720SGraeme Russ #ifndef __ASM_PROCESSOR_H_ 8fea25720SGraeme Russ #define __ASM_PROCESSOR_H_ 1 9fea25720SGraeme Russ 10109ad143SGraeme Russ #define X86_GDT_ENTRY_SIZE 8 11109ad143SGraeme Russ 12e34aef1dSSimon Glass #define X86_GDT_ENTRY_NULL 0 13e34aef1dSSimon Glass #define X86_GDT_ENTRY_UNUSED 1 14e34aef1dSSimon Glass #define X86_GDT_ENTRY_32BIT_CS 2 15109ad143SGraeme Russ #define X86_GDT_ENTRY_32BIT_DS 3 16e34aef1dSSimon Glass #define X86_GDT_ENTRY_32BIT_FS 4 17e34aef1dSSimon Glass #define X86_GDT_ENTRY_16BIT_CS 5 18e34aef1dSSimon Glass #define X86_GDT_ENTRY_16BIT_DS 6 19e34aef1dSSimon Glass #define X86_GDT_ENTRY_16BIT_FLAT_CS 7 20e34aef1dSSimon Glass #define X86_GDT_ENTRY_16BIT_FLAT_DS 8 21e34aef1dSSimon Glass #define X86_GDT_NUM_ENTRIES 9 22109ad143SGraeme Russ 23109ad143SGraeme Russ #define X86_GDT_SIZE (X86_GDT_NUM_ENTRIES * X86_GDT_ENTRY_SIZE) 24fea25720SGraeme Russ 2545b5a378SSimon Glass /* Length of the public header on Intel microcode blobs */ 2645b5a378SSimon Glass #define UCODE_HEADER_LEN 0x30 2745b5a378SSimon Glass 2821b9b14bSSimon Glass #ifndef __ASSEMBLY__ 2921b9b14bSSimon Glass 30ff6a8f3cSSimon Glass /* 31ff6a8f3cSSimon Glass * This register is documented in (for example) the Intel Atom Processor E3800 32ff6a8f3cSSimon Glass * Product Family Datasheet in "PCU - Power Management Controller (PMC)". 33ff6a8f3cSSimon Glass * 34ff6a8f3cSSimon Glass * RST_CNT: Reset Control Register (RST_CNT) Offset cf9. 35ff6a8f3cSSimon Glass * 36ff6a8f3cSSimon Glass * The naming follows Intel's naming. 37ff6a8f3cSSimon Glass */ 382a605d4dSSimon Glass #define IO_PORT_RESET 0xcf9 39f5fbbe95SSimon Glass 40ff6a8f3cSSimon Glass enum { 41ff6a8f3cSSimon Glass SYS_RST = 1 << 1, /* 0 for soft reset, 1 for hard reset */ 42ff6a8f3cSSimon Glass RST_CPU = 1 << 2, /* initiate reset */ 43ff6a8f3cSSimon Glass FULL_RST = 1 << 3, /* full power cycle */ 44ff6a8f3cSSimon Glass }; 45ff6a8f3cSSimon Glass cpu_hlt(void)4621b9b14bSSimon Glassstatic inline __attribute__((always_inline)) void cpu_hlt(void) 4721b9b14bSSimon Glass { 4821b9b14bSSimon Glass asm("hlt"); 4921b9b14bSSimon Glass } 5021b9b14bSSimon Glass cpu_get_sp(void)5121b9b14bSSimon Glassstatic inline ulong cpu_get_sp(void) 5221b9b14bSSimon Glass { 5321b9b14bSSimon Glass ulong result; 5421b9b14bSSimon Glass 5521b9b14bSSimon Glass asm volatile( 5621b9b14bSSimon Glass "mov %%esp, %%eax" 5721b9b14bSSimon Glass : "=a" (result)); 5821b9b14bSSimon Glass return result; 5921b9b14bSSimon Glass } 6021b9b14bSSimon Glass 6121b9b14bSSimon Glass #endif /* __ASSEMBLY__ */ 6221b9b14bSSimon Glass 63fea25720SGraeme Russ #endif 64