1*fea25720SGraeme Russ #ifndef _ASM_X86_PROCESSOR_FLAGS_H 2*fea25720SGraeme Russ #define _ASM_X86_PROCESSOR_FLAGS_H 3*fea25720SGraeme Russ /* Various flags defined: can be included from assembler. */ 4*fea25720SGraeme Russ 5*fea25720SGraeme Russ /* 6*fea25720SGraeme Russ * EFLAGS bits 7*fea25720SGraeme Russ */ 8*fea25720SGraeme Russ #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */ 9*fea25720SGraeme Russ #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */ 10*fea25720SGraeme Russ #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */ 11*fea25720SGraeme Russ #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */ 12*fea25720SGraeme Russ #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */ 13*fea25720SGraeme Russ #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */ 14*fea25720SGraeme Russ #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */ 15*fea25720SGraeme Russ #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */ 16*fea25720SGraeme Russ #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */ 17*fea25720SGraeme Russ #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */ 18*fea25720SGraeme Russ #define X86_EFLAGS_NT 0x00004000 /* Nested Task */ 19*fea25720SGraeme Russ #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */ 20*fea25720SGraeme Russ #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */ 21*fea25720SGraeme Russ #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */ 22*fea25720SGraeme Russ #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */ 23*fea25720SGraeme Russ #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */ 24*fea25720SGraeme Russ #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */ 25*fea25720SGraeme Russ 26*fea25720SGraeme Russ /* 27*fea25720SGraeme Russ * Basic CPU control in CR0 28*fea25720SGraeme Russ */ 29*fea25720SGraeme Russ #define X86_CR0_PE 0x00000001 /* Protection Enable */ 30*fea25720SGraeme Russ #define X86_CR0_MP 0x00000002 /* Monitor Coprocessor */ 31*fea25720SGraeme Russ #define X86_CR0_EM 0x00000004 /* Emulation */ 32*fea25720SGraeme Russ #define X86_CR0_TS 0x00000008 /* Task Switched */ 33*fea25720SGraeme Russ #define X86_CR0_ET 0x00000010 /* Extension Type */ 34*fea25720SGraeme Russ #define X86_CR0_NE 0x00000020 /* Numeric Error */ 35*fea25720SGraeme Russ #define X86_CR0_WP 0x00010000 /* Write Protect */ 36*fea25720SGraeme Russ #define X86_CR0_AM 0x00040000 /* Alignment Mask */ 37*fea25720SGraeme Russ #define X86_CR0_NW 0x20000000 /* Not Write-through */ 38*fea25720SGraeme Russ #define X86_CR0_CD 0x40000000 /* Cache Disable */ 39*fea25720SGraeme Russ #define X86_CR0_PG 0x80000000 /* Paging */ 40*fea25720SGraeme Russ 41*fea25720SGraeme Russ /* 42*fea25720SGraeme Russ * Paging options in CR3 43*fea25720SGraeme Russ */ 44*fea25720SGraeme Russ #define X86_CR3_PWT 0x00000008 /* Page Write Through */ 45*fea25720SGraeme Russ #define X86_CR3_PCD 0x00000010 /* Page Cache Disable */ 46*fea25720SGraeme Russ 47*fea25720SGraeme Russ /* 48*fea25720SGraeme Russ * Intel CPU features in CR4 49*fea25720SGraeme Russ */ 50*fea25720SGraeme Russ #define X86_CR4_VME 0x00000001 /* enable vm86 extensions */ 51*fea25720SGraeme Russ #define X86_CR4_PVI 0x00000002 /* virtual interrupts flag enable */ 52*fea25720SGraeme Russ #define X86_CR4_TSD 0x00000004 /* disable time stamp at ipl 3 */ 53*fea25720SGraeme Russ #define X86_CR4_DE 0x00000008 /* enable debugging extensions */ 54*fea25720SGraeme Russ #define X86_CR4_PSE 0x00000010 /* enable page size extensions */ 55*fea25720SGraeme Russ #define X86_CR4_PAE 0x00000020 /* enable physical address extensions */ 56*fea25720SGraeme Russ #define X86_CR4_MCE 0x00000040 /* Machine check enable */ 57*fea25720SGraeme Russ #define X86_CR4_PGE 0x00000080 /* enable global pages */ 58*fea25720SGraeme Russ #define X86_CR4_PCE 0x00000100 /* enable performance counters at ipl 3 */ 59*fea25720SGraeme Russ #define X86_CR4_OSFXSR 0x00000200 /* enable fast FPU save and restore */ 60*fea25720SGraeme Russ #define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */ 61*fea25720SGraeme Russ #define X86_CR4_VMXE 0x00002000 /* enable VMX virtualization */ 62*fea25720SGraeme Russ #define X86_CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */ 63*fea25720SGraeme Russ 64*fea25720SGraeme Russ /* 65*fea25720SGraeme Russ * x86-64 Task Priority Register, CR8 66*fea25720SGraeme Russ */ 67*fea25720SGraeme Russ #define X86_CR8_TPR 0x0000000F /* task priority register */ 68*fea25720SGraeme Russ 69*fea25720SGraeme Russ /* 70*fea25720SGraeme Russ * AMD and Transmeta use MSRs for configuration; see <asm/msr-index.h> 71*fea25720SGraeme Russ */ 72*fea25720SGraeme Russ 73*fea25720SGraeme Russ /* 74*fea25720SGraeme Russ * NSC/Cyrix CPU configuration register indexes 75*fea25720SGraeme Russ */ 76*fea25720SGraeme Russ #define CX86_PCR0 0x20 77*fea25720SGraeme Russ #define CX86_GCR 0xb8 78*fea25720SGraeme Russ #define CX86_CCR0 0xc0 79*fea25720SGraeme Russ #define CX86_CCR1 0xc1 80*fea25720SGraeme Russ #define CX86_CCR2 0xc2 81*fea25720SGraeme Russ #define CX86_CCR3 0xc3 82*fea25720SGraeme Russ #define CX86_CCR4 0xe8 83*fea25720SGraeme Russ #define CX86_CCR5 0xe9 84*fea25720SGraeme Russ #define CX86_CCR6 0xea 85*fea25720SGraeme Russ #define CX86_CCR7 0xeb 86*fea25720SGraeme Russ #define CX86_PCR1 0xf0 87*fea25720SGraeme Russ #define CX86_DIR0 0xfe 88*fea25720SGraeme Russ #define CX86_DIR1 0xff 89*fea25720SGraeme Russ #define CX86_ARR_BASE 0xc4 90*fea25720SGraeme Russ #define CX86_RCR_BASE 0xdc 91*fea25720SGraeme Russ 92*fea25720SGraeme Russ #ifdef __KERNEL__ 93*fea25720SGraeme Russ #ifdef CONFIG_VM86 94*fea25720SGraeme Russ #define X86_VM_MASK X86_EFLAGS_VM 95*fea25720SGraeme Russ #else 96*fea25720SGraeme Russ #define X86_VM_MASK 0 /* No VM86 support */ 97*fea25720SGraeme Russ #endif 98*fea25720SGraeme Russ #endif 99*fea25720SGraeme Russ 100*fea25720SGraeme Russ #endif /* _ASM_X86_PROCESSOR_FLAGS_H */ 101