1fea25720SGraeme Russ /* 2fea25720SGraeme Russ * (C) Copyright 2002 3fa82f871SAlbert ARIBAUD * Daniel Engström, Omicron Ceti AB, daniel@omicron.se 4fea25720SGraeme Russ * 51a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 6fea25720SGraeme Russ */ 7fea25720SGraeme Russ 8fea25720SGraeme Russ #ifndef _PCI_I386_H_ 9452f50f7SGabe Black #define _PCI_I386_H_ 10fea25720SGraeme Russ 11*a219daeaSSimon Glass #include <pci.h> 12*a219daeaSSimon Glass 133c8ae536SBin Meng /* bus mapping constants (used for PCI core initialization) */ 143c8ae536SBin Meng #define PCI_REG_ADDR 0xcf8 153c8ae536SBin Meng #define PCI_REG_DATA 0xcfc 163c8ae536SBin Meng 173c8ae536SBin Meng #define PCI_CFG_EN 0x80000000 183c8ae536SBin Meng 193c8ae536SBin Meng #ifndef __ASSEMBLY__ 203c8ae536SBin Meng 2183088afbSGraeme Russ #define DEFINE_PCI_DEVICE_TABLE(_table) \ 2283088afbSGraeme Russ const struct pci_device_id _table[] 2383088afbSGraeme Russ 24d188b18fSSimon Glass struct pci_controller; 25d188b18fSSimon Glass 261cfcf037SGraeme Russ void pci_setup_type1(struct pci_controller *hose); 27d188b18fSSimon Glass 28d188b18fSSimon Glass /** 29d188b18fSSimon Glass * board_pci_setup_hose() - Set up the PCI hose 30d188b18fSSimon Glass * 31d188b18fSSimon Glass * This is called by the common x86 PCI code to set up the PCI controller 32d188b18fSSimon Glass * hose. It may be called when no memory/BSS is available so should just 33d188b18fSSimon Glass * store things in 'hose' and not in BSS variables. 34d188b18fSSimon Glass */ 35d188b18fSSimon Glass void board_pci_setup_hose(struct pci_controller *hose); 367430f108SSimon Glass 377430f108SSimon Glass /** 387430f108SSimon Glass * pci_early_init_hose() - Set up PCI host before relocation 397430f108SSimon Glass * 407430f108SSimon Glass * This allocates memory for, sets up and returns the PCI hose. It can be 418f9052fdSBin Meng * called before relocation. The hose will be stored in gd->hose for 427430f108SSimon Glass * later use, but will become invalid one DRAM is available. 437430f108SSimon Glass */ 447430f108SSimon Glass int pci_early_init_hose(struct pci_controller **hosep); 456fb3b72eSSimon Glass 46e94ea6f6SSimon Glass int board_pci_pre_scan(struct pci_controller *hose); 47e94ea6f6SSimon Glass int board_pci_post_scan(struct pci_controller *hose); 48e94ea6f6SSimon Glass 496fb3b72eSSimon Glass /* 506fb3b72eSSimon Glass * Simple PCI access routines - these work from either the early PCI hose 516fb3b72eSSimon Glass * or the 'real' one, created after U-Boot has memory available 526fb3b72eSSimon Glass */ 5331f57c28SSimon Glass unsigned int x86_pci_read_config8(pci_dev_t dev, unsigned where); 5431f57c28SSimon Glass unsigned int x86_pci_read_config16(pci_dev_t dev, unsigned where); 5531f57c28SSimon Glass unsigned int x86_pci_read_config32(pci_dev_t dev, unsigned where); 566fb3b72eSSimon Glass 5731f57c28SSimon Glass void x86_pci_write_config8(pci_dev_t dev, unsigned where, unsigned value); 5831f57c28SSimon Glass void x86_pci_write_config16(pci_dev_t dev, unsigned where, unsigned value); 5931f57c28SSimon Glass void x86_pci_write_config32(pci_dev_t dev, unsigned where, unsigned value); 606fb3b72eSSimon Glass 61*a219daeaSSimon Glass int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset, 62*a219daeaSSimon Glass ulong *valuep, enum pci_size_t size); 63*a219daeaSSimon Glass 64*a219daeaSSimon Glass int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset, 65*a219daeaSSimon Glass ulong value, enum pci_size_t size); 66*a219daeaSSimon Glass 673c8ae536SBin Meng #endif /* __ASSEMBLY__ */ 683c8ae536SBin Meng 693c8ae536SBin Meng #endif /* _PCI_I386_H_ */ 70