1fea25720SGraeme Russ /* 2fea25720SGraeme Russ * (C) Copyright 2002 3fa82f871SAlbert ARIBAUD * Daniel Engström, Omicron Ceti AB, daniel@omicron.se 4fea25720SGraeme Russ * 51a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 6fea25720SGraeme Russ */ 7fea25720SGraeme Russ 8fea25720SGraeme Russ #ifndef _PCI_I386_H_ 9452f50f7SGabe Black #define _PCI_I386_H_ 10fea25720SGraeme Russ 11*3c8ae536SBin Meng /* bus mapping constants (used for PCI core initialization) */ 12*3c8ae536SBin Meng #define PCI_REG_ADDR 0xcf8 13*3c8ae536SBin Meng #define PCI_REG_DATA 0xcfc 14*3c8ae536SBin Meng 15*3c8ae536SBin Meng #define PCI_CFG_EN 0x80000000 16*3c8ae536SBin Meng 17*3c8ae536SBin Meng #ifndef __ASSEMBLY__ 18*3c8ae536SBin Meng 1983088afbSGraeme Russ #define DEFINE_PCI_DEVICE_TABLE(_table) \ 2083088afbSGraeme Russ const struct pci_device_id _table[] 2183088afbSGraeme Russ 22d188b18fSSimon Glass struct pci_controller; 23d188b18fSSimon Glass 241cfcf037SGraeme Russ void pci_setup_type1(struct pci_controller *hose); 25d188b18fSSimon Glass 26d188b18fSSimon Glass /** 27d188b18fSSimon Glass * board_pci_setup_hose() - Set up the PCI hose 28d188b18fSSimon Glass * 29d188b18fSSimon Glass * This is called by the common x86 PCI code to set up the PCI controller 30d188b18fSSimon Glass * hose. It may be called when no memory/BSS is available so should just 31d188b18fSSimon Glass * store things in 'hose' and not in BSS variables. 32d188b18fSSimon Glass */ 33d188b18fSSimon Glass void board_pci_setup_hose(struct pci_controller *hose); 347430f108SSimon Glass 357430f108SSimon Glass /** 367430f108SSimon Glass * pci_early_init_hose() - Set up PCI host before relocation 377430f108SSimon Glass * 387430f108SSimon Glass * This allocates memory for, sets up and returns the PCI hose. It can be 398f9052fdSBin Meng * called before relocation. The hose will be stored in gd->hose for 407430f108SSimon Glass * later use, but will become invalid one DRAM is available. 417430f108SSimon Glass */ 427430f108SSimon Glass int pci_early_init_hose(struct pci_controller **hosep); 436fb3b72eSSimon Glass 44e94ea6f6SSimon Glass int board_pci_pre_scan(struct pci_controller *hose); 45e94ea6f6SSimon Glass int board_pci_post_scan(struct pci_controller *hose); 46e94ea6f6SSimon Glass 476fb3b72eSSimon Glass /* 486fb3b72eSSimon Glass * Simple PCI access routines - these work from either the early PCI hose 496fb3b72eSSimon Glass * or the 'real' one, created after U-Boot has memory available 506fb3b72eSSimon Glass */ 516fb3b72eSSimon Glass unsigned int pci_read_config8(pci_dev_t dev, unsigned where); 526fb3b72eSSimon Glass unsigned int pci_read_config16(pci_dev_t dev, unsigned where); 536fb3b72eSSimon Glass unsigned int pci_read_config32(pci_dev_t dev, unsigned where); 546fb3b72eSSimon Glass 556fb3b72eSSimon Glass void pci_write_config8(pci_dev_t dev, unsigned where, unsigned value); 566fb3b72eSSimon Glass void pci_write_config16(pci_dev_t dev, unsigned where, unsigned value); 576fb3b72eSSimon Glass void pci_write_config32(pci_dev_t dev, unsigned where, unsigned value); 586fb3b72eSSimon Glass 59*3c8ae536SBin Meng #endif /* __ASSEMBLY__ */ 60*3c8ae536SBin Meng 61*3c8ae536SBin Meng #endif /* _PCI_I386_H_ */ 62