1 /* 2 * Copyright (c) 2016 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef __asm_pch_common_h 8 #define __asm_pch_common_h 9 10 /* Common Intel SATA registers */ 11 #define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ 12 #define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ 13 #define SATA_SP 0xd0 /* Scratchpad */ 14 15 #define INTR_LN 0x3c 16 #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ 17 #define IDE_DECODE_ENABLE (1 << 15) 18 #define IDE_SITRE (1 << 14) 19 #define IDE_ISP_5_CLOCKS (0 << 12) 20 #define IDE_ISP_4_CLOCKS (1 << 12) 21 #define IDE_ISP_3_CLOCKS (2 << 12) 22 #define IDE_RCT_4_CLOCKS (0 << 8) 23 #define IDE_RCT_3_CLOCKS (1 << 8) 24 #define IDE_RCT_2_CLOCKS (2 << 8) 25 #define IDE_RCT_1_CLOCKS (3 << 8) 26 #define IDE_DTE1 (1 << 7) 27 #define IDE_PPE1 (1 << 6) 28 #define IDE_IE1 (1 << 5) 29 #define IDE_TIME1 (1 << 4) 30 #define IDE_DTE0 (1 << 3) 31 #define IDE_PPE0 (1 << 2) 32 #define IDE_IE0 (1 << 1) 33 #define IDE_TIME0 (1 << 0) 34 #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ 35 36 #define SERIRQ_CNTL 0x64 37 38 /** 39 * pch_common_sir_read() - Read from a SATA indexed register 40 * 41 * @dev: SATA device 42 * @idx: Register index to read 43 * @return value read from register 44 */ 45 u32 pch_common_sir_read(struct udevice *dev, int idx); 46 47 /** 48 * pch_common_sir_write() - Write to a SATA indexed register 49 * 50 * @dev: SATA device 51 * @idx: Register index to write 52 * @value: Value to write 53 */ 54 void pch_common_sir_write(struct udevice *dev, int idx, u32 value); 55 56 #endif 57