1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (c) 2014 Google, Inc 4 * 5 * From Coreboot file of the same name 6 */ 7 8 #ifndef _ASM_MTRR_H 9 #define _ASM_MTRR_H 10 11 /* MTRR region types */ 12 #define MTRR_TYPE_UNCACHEABLE 0 13 #define MTRR_TYPE_WRCOMB 1 14 #define MTRR_TYPE_WRTHROUGH 4 15 #define MTRR_TYPE_WRPROT 5 16 #define MTRR_TYPE_WRBACK 6 17 18 #define MTRR_TYPE_COUNT 7 19 20 #define MTRR_CAP_MSR 0x0fe 21 #define MTRR_DEF_TYPE_MSR 0x2ff 22 23 #define MTRR_CAP_SMRR (1 << 11) 24 #define MTRR_CAP_WC (1 << 10) 25 #define MTRR_CAP_FIX (1 << 8) 26 #define MTRR_CAP_VCNT_MASK 0xff 27 28 #define MTRR_DEF_TYPE_EN (1 << 11) 29 #define MTRR_DEF_TYPE_FIX_EN (1 << 10) 30 31 #define MTRR_PHYS_BASE_MSR(reg) (0x200 + 2 * (reg)) 32 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) 33 34 #define MTRR_PHYS_MASK_VALID (1 << 11) 35 36 #define MTRR_BASE_TYPE_MASK 0x7 37 38 /* Number of MTRRs supported */ 39 #define MTRR_COUNT 8 40 41 #define NUM_FIXED_MTRRS 11 42 #define RANGES_PER_FIXED_MTRR 8 43 #define NUM_FIXED_RANGES (NUM_FIXED_MTRRS * RANGES_PER_FIXED_MTRR) 44 45 #define MTRR_FIX_64K_00000_MSR 0x250 46 #define MTRR_FIX_16K_80000_MSR 0x258 47 #define MTRR_FIX_16K_A0000_MSR 0x259 48 #define MTRR_FIX_4K_C0000_MSR 0x268 49 #define MTRR_FIX_4K_C8000_MSR 0x269 50 #define MTRR_FIX_4K_D0000_MSR 0x26a 51 #define MTRR_FIX_4K_D8000_MSR 0x26b 52 #define MTRR_FIX_4K_E0000_MSR 0x26c 53 #define MTRR_FIX_4K_E8000_MSR 0x26d 54 #define MTRR_FIX_4K_F0000_MSR 0x26e 55 #define MTRR_FIX_4K_F8000_MSR 0x26f 56 57 #define MTRR_FIX_TYPE(t) ((t << 24) | (t << 16) | (t << 8) | t) 58 59 #if !defined(__ASSEMBLER__) 60 61 /** 62 * Information about the previous MTRR state, set up by mtrr_open() 63 * 64 * @deftype: Previous value of MTRR_DEF_TYPE_MSR 65 * @enable_cache: true if cache was enabled 66 */ 67 struct mtrr_state { 68 uint64_t deftype; 69 bool enable_cache; 70 }; 71 72 /** 73 * mtrr_open() - Prepare to adjust MTRRs 74 * 75 * Use mtrr_open() passing in a structure - this function will init it. Then 76 * when done, pass the same structure to mtrr_close() to re-enable MTRRs and 77 * possibly the cache. 78 * 79 * @state: Empty structure to pass in to hold settings 80 * @do_caches: true to disable caches before opening 81 */ 82 void mtrr_open(struct mtrr_state *state, bool do_caches); 83 84 /** 85 * mtrr_open() - Clean up after adjusting MTRRs, and enable them 86 * 87 * This uses the structure containing information returned from mtrr_open(). 88 * 89 * @state: Structure from mtrr_open() 90 * @state: true to restore cache state to that before mtrr_open() 91 */ 92 void mtrr_close(struct mtrr_state *state, bool do_caches); 93 94 /** 95 * mtrr_add_request() - Add a new MTRR request 96 * 97 * This adds a request for a memory region to be set up in a particular way. 98 * 99 * @type: Requested type (MTRR_TYPE_) 100 * @start: Start address 101 * @size: Size 102 * 103 * @return: 0 on success, non-zero on failure 104 */ 105 int mtrr_add_request(int type, uint64_t start, uint64_t size); 106 107 /** 108 * mtrr_commit() - set up the MTRR registers based on current requests 109 * 110 * This sets up MTRRs for the available DRAM and the requests received so far. 111 * It must be called with caches disabled. 112 * 113 * @do_caches: true if caches are currently on 114 * 115 * @return: 0 on success, non-zero on failure 116 */ 117 int mtrr_commit(bool do_caches); 118 119 #endif 120 121 #if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0) 122 # error "CONFIG_XIP_ROM_SIZE is not a power of 2" 123 #endif 124 125 #if ((CONFIG_CACHE_ROM_SIZE & (CONFIG_CACHE_ROM_SIZE - 1)) != 0) 126 # error "CONFIG_CACHE_ROM_SIZE is not a power of 2" 127 #endif 128 129 #define CACHE_ROM_BASE (((1 << 20) - (CONFIG_CACHE_ROM_SIZE >> 12)) << 12) 130 131 #endif 132