1 /* 2 * Copyright (c) 2014 Google, Inc 3 * 4 * From Coreboot file of the same name 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef _ASM_MTRR_H 10 #define _ASM_MTRR_H 11 12 /* MTRR region types */ 13 #define MTRR_TYPE_UNCACHEABLE 0 14 #define MTRR_TYPE_WRCOMB 1 15 #define MTRR_TYPE_WRTHROUGH 4 16 #define MTRR_TYPE_WRPROT 5 17 #define MTRR_TYPE_WRBACK 6 18 19 #define MTRR_TYPE_COUNT 7 20 21 #define MTRR_CAP_MSR 0x0fe 22 #define MTRR_DEF_TYPE_MSR 0x2ff 23 24 #define MTRR_CAP_SMRR (1 << 11) 25 #define MTRR_CAP_WC (1 << 10) 26 #define MTRR_CAP_FIX (1 << 8) 27 #define MTRR_CAP_VCNT_MASK 0xff 28 29 #define MTRR_DEF_TYPE_EN (1 << 11) 30 #define MTRR_DEF_TYPE_FIX_EN (1 << 10) 31 32 #define MTRR_PHYS_BASE_MSR(reg) (0x200 + 2 * (reg)) 33 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) 34 35 #define MTRR_PHYS_MASK_VALID (1 << 11) 36 37 #define MTRR_BASE_TYPE_MASK 0x7 38 39 /* Number of MTRRs supported */ 40 #define MTRR_COUNT 8 41 42 #define NUM_FIXED_MTRRS 11 43 #define RANGES_PER_FIXED_MTRR 8 44 #define NUM_FIXED_RANGES (NUM_FIXED_MTRRS * RANGES_PER_FIXED_MTRR) 45 46 #define MTRR_FIX_64K_00000_MSR 0x250 47 #define MTRR_FIX_16K_80000_MSR 0x258 48 #define MTRR_FIX_16K_A0000_MSR 0x259 49 #define MTRR_FIX_4K_C0000_MSR 0x268 50 #define MTRR_FIX_4K_C8000_MSR 0x269 51 #define MTRR_FIX_4K_D0000_MSR 0x26a 52 #define MTRR_FIX_4K_D8000_MSR 0x26b 53 #define MTRR_FIX_4K_E0000_MSR 0x26c 54 #define MTRR_FIX_4K_E8000_MSR 0x26d 55 #define MTRR_FIX_4K_F0000_MSR 0x26e 56 #define MTRR_FIX_4K_F8000_MSR 0x26f 57 58 #define MTRR_FIX_TYPE(t) ((t << 24) | (t << 16) | (t << 8) | t) 59 60 #if !defined(__ASSEMBLER__) 61 62 /** 63 * Information about the previous MTRR state, set up by mtrr_open() 64 * 65 * @deftype: Previous value of MTRR_DEF_TYPE_MSR 66 * @enable_cache: true if cache was enabled 67 */ 68 struct mtrr_state { 69 uint64_t deftype; 70 bool enable_cache; 71 }; 72 73 /** 74 * mtrr_open() - Prepare to adjust MTRRs 75 * 76 * Use mtrr_open() passing in a structure - this function will init it. Then 77 * when done, pass the same structure to mtrr_close() to re-enable MTRRs and 78 * possibly the cache. 79 * 80 * @state: Empty structure to pass in to hold settings 81 */ 82 void mtrr_open(struct mtrr_state *state); 83 84 /** 85 * mtrr_open() - Clean up after adjusting MTRRs, and enable them 86 * 87 * This uses the structure containing information returned from mtrr_open(). 88 * 89 * @state: Structure from mtrr_open() 90 */ 91 void mtrr_close(struct mtrr_state *state); 92 93 /** 94 * mtrr_add_request() - Add a new MTRR request 95 * 96 * This adds a request for a memory region to be set up in a particular way. 97 * 98 * @type: Requested type (MTRR_TYPE_) 99 * @start: Start address 100 * @size: Size 101 * 102 * @return: 0 on success, non-zero on failure 103 */ 104 int mtrr_add_request(int type, uint64_t start, uint64_t size); 105 106 /** 107 * mtrr_commit() - set up the MTRR registers based on current requests 108 * 109 * This sets up MTRRs for the available DRAM and the requests received so far. 110 * It must be called with caches disabled. 111 * 112 * @do_caches: true if caches are currently on 113 * 114 * @return: 0 on success, non-zero on failure 115 */ 116 int mtrr_commit(bool do_caches); 117 118 #endif 119 120 #if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0) 121 # error "CONFIG_XIP_ROM_SIZE is not a power of 2" 122 #endif 123 124 #if ((CONFIG_CACHE_ROM_SIZE & (CONFIG_CACHE_ROM_SIZE - 1)) != 0) 125 # error "CONFIG_CACHE_ROM_SIZE is not a power of 2" 126 #endif 127 128 #define CACHE_ROM_BASE (((1 << 20) - (CONFIG_CACHE_ROM_SIZE >> 12)) << 12) 129 130 #endif 131