1 /* 2 * Copyright (c) 2014 Google, Inc 3 * 4 * From Coreboot file of the same name 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef _ASM_MTRR_H 10 #define _ASM_MTRR_H 11 12 /* MTRR region types */ 13 #define MTRR_TYPE_UNCACHEABLE 0 14 #define MTRR_TYPE_WRCOMB 1 15 #define MTRR_TYPE_WRTHROUGH 4 16 #define MTRR_TYPE_WRPROT 5 17 #define MTRR_TYPE_WRBACK 6 18 19 #define MTRR_TYPE_COUNT 7 20 21 #define MTRR_CAP_MSR 0x0fe 22 #define MTRR_DEF_TYPE_MSR 0x2ff 23 24 #define MTRR_DEF_TYPE_EN (1 << 11) 25 #define MTRR_DEF_TYPE_FIX_EN (1 << 10) 26 27 #define MTRR_PHYS_BASE_MSR(reg) (0x200 + 2 * (reg)) 28 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) 29 30 #define MTRR_PHYS_MASK_VALID (1 << 11) 31 32 #define MTRR_BASE_TYPE_MASK 0x7 33 34 /* Number of MTRRs supported */ 35 #define MTRR_COUNT 8 36 37 #define NUM_FIXED_MTRRS 11 38 #define RANGES_PER_FIXED_MTRR 8 39 #define NUM_FIXED_RANGES (NUM_FIXED_MTRRS * RANGES_PER_FIXED_MTRR) 40 41 #define MTRR_FIX_64K_00000_MSR 0x250 42 #define MTRR_FIX_16K_80000_MSR 0x258 43 #define MTRR_FIX_16K_A0000_MSR 0x259 44 #define MTRR_FIX_4K_C0000_MSR 0x268 45 #define MTRR_FIX_4K_C8000_MSR 0x269 46 #define MTRR_FIX_4K_D0000_MSR 0x26a 47 #define MTRR_FIX_4K_D8000_MSR 0x26b 48 #define MTRR_FIX_4K_E0000_MSR 0x26c 49 #define MTRR_FIX_4K_E8000_MSR 0x26d 50 #define MTRR_FIX_4K_F0000_MSR 0x26e 51 #define MTRR_FIX_4K_F8000_MSR 0x26f 52 53 #if !defined(__ASSEMBLER__) 54 55 /** 56 * Information about the previous MTRR state, set up by mtrr_open() 57 * 58 * @deftype: Previous value of MTRR_DEF_TYPE_MSR 59 * @enable_cache: true if cache was enabled 60 */ 61 struct mtrr_state { 62 uint64_t deftype; 63 bool enable_cache; 64 }; 65 66 /** 67 * mtrr_open() - Prepare to adjust MTRRs 68 * 69 * Use mtrr_open() passing in a structure - this function will init it. Then 70 * when done, pass the same structure to mtrr_close() to re-enable MTRRs and 71 * possibly the cache. 72 * 73 * @state: Empty structure to pass in to hold settings 74 */ 75 void mtrr_open(struct mtrr_state *state); 76 77 /** 78 * mtrr_open() - Clean up after adjusting MTRRs, and enable them 79 * 80 * This uses the structure containing information returned from mtrr_open(). 81 * 82 * @state: Structure from mtrr_open() 83 */ 84 void mtrr_close(struct mtrr_state *state); 85 86 /** 87 * mtrr_add_request() - Add a new MTRR request 88 * 89 * This adds a request for a memory region to be set up in a particular way. 90 * 91 * @type: Requested type (MTRR_TYPE_) 92 * @start: Start address 93 * @size: Size 94 * 95 * @return: 0 on success, non-zero on failure 96 */ 97 int mtrr_add_request(int type, uint64_t start, uint64_t size); 98 99 /** 100 * mtrr_commit() - set up the MTRR registers based on current requests 101 * 102 * This sets up MTRRs for the available DRAM and the requests received so far. 103 * It must be called with caches disabled. 104 * 105 * @do_caches: true if caches are currently on 106 * 107 * @return: 0 on success, non-zero on failure 108 */ 109 int mtrr_commit(bool do_caches); 110 111 #endif 112 113 #if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0) 114 # error "CONFIG_XIP_ROM_SIZE is not a power of 2" 115 #endif 116 117 #if ((CONFIG_CACHE_ROM_SIZE & (CONFIG_CACHE_ROM_SIZE - 1)) != 0) 118 # error "CONFIG_CACHE_ROM_SIZE is not a power of 2" 119 #endif 120 121 #define CACHE_ROM_BASE (((1 << 20) - (CONFIG_CACHE_ROM_SIZE >> 12)) << 12) 122 123 #endif 124