1 /* 2 * Copyright (c) 2014 Google, Inc 3 * 4 * From Coreboot file of the same name 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef _ASM_MTRR_H 10 #define _ASM_MTRR_H 11 12 /* MTRR region types */ 13 #define MTRR_TYPE_UNCACHEABLE 0 14 #define MTRR_TYPE_WRCOMB 1 15 #define MTRR_TYPE_WRTHROUGH 4 16 #define MTRR_TYPE_WRPROT 5 17 #define MTRR_TYPE_WRBACK 6 18 19 #define MTRR_TYPE_COUNT 7 20 21 #define MTRR_CAP_MSR 0x0fe 22 #define MTRR_DEF_TYPE_MSR 0x2ff 23 24 #define MTRR_DEF_TYPE_EN (1 << 11) 25 #define MTRR_DEF_TYPE_FIX_EN (1 << 10) 26 27 #define MTRR_PHYS_BASE_MSR(reg) (0x200 + 2 * (reg)) 28 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) 29 30 #define MTRR_PHYS_MASK_VALID (1 << 11) 31 32 #define MTRR_BASE_TYPE_MASK 0x7 33 34 /* Number of MTRRs supported */ 35 #define MTRR_COUNT 8 36 37 #define NUM_FIXED_RANGES 88 38 #define RANGES_PER_FIXED_MTRR 8 39 #define MTRR_FIX_64K_00000_MSR 0x250 40 #define MTRR_FIX_16K_80000_MSR 0x258 41 #define MTRR_FIX_16K_A0000_MSR 0x259 42 #define MTRR_FIX_4K_C0000_MSR 0x268 43 #define MTRR_FIX_4K_C8000_MSR 0x269 44 #define MTRR_FIX_4K_D0000_MSR 0x26a 45 #define MTRR_FIX_4K_D8000_MSR 0x26b 46 #define MTRR_FIX_4K_E0000_MSR 0x26c 47 #define MTRR_FIX_4K_E8000_MSR 0x26d 48 #define MTRR_FIX_4K_F0000_MSR 0x26e 49 #define MTRR_FIX_4K_F8000_MSR 0x26f 50 51 #if !defined(__ASSEMBLER__) 52 53 /** 54 * Information about the previous MTRR state, set up by mtrr_open() 55 * 56 * @deftype: Previous value of MTRR_DEF_TYPE_MSR 57 * @enable_cache: true if cache was enabled 58 */ 59 struct mtrr_state { 60 uint64_t deftype; 61 bool enable_cache; 62 }; 63 64 /** 65 * mtrr_open() - Prepare to adjust MTRRs 66 * 67 * Use mtrr_open() passing in a structure - this function will init it. Then 68 * when done, pass the same structure to mtrr_close() to re-enable MTRRs and 69 * possibly the cache. 70 * 71 * @state: Empty structure to pass in to hold settings 72 */ 73 void mtrr_open(struct mtrr_state *state); 74 75 /** 76 * mtrr_open() - Clean up after adjusting MTRRs, and enable them 77 * 78 * This uses the structure containing information returned from mtrr_open(). 79 * 80 * @state: Structure from mtrr_open() 81 */ 82 void mtrr_close(struct mtrr_state *state); 83 84 /** 85 * mtrr_add_request() - Add a new MTRR request 86 * 87 * This adds a request for a memory region to be set up in a particular way. 88 * 89 * @type: Requested type (MTRR_TYPE_) 90 * @start: Start address 91 * @size: Size 92 * 93 * @return: 0 on success, non-zero on failure 94 */ 95 int mtrr_add_request(int type, uint64_t start, uint64_t size); 96 97 /** 98 * mtrr_commit() - set up the MTRR registers based on current requests 99 * 100 * This sets up MTRRs for the available DRAM and the requests received so far. 101 * It must be called with caches disabled. 102 * 103 * @do_caches: true if caches are currently on 104 * 105 * @return: 0 on success, non-zero on failure 106 */ 107 int mtrr_commit(bool do_caches); 108 109 #endif 110 111 #if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0) 112 # error "CONFIG_XIP_ROM_SIZE is not a power of 2" 113 #endif 114 115 #if ((CONFIG_CACHE_ROM_SIZE & (CONFIG_CACHE_ROM_SIZE - 1)) != 0) 116 # error "CONFIG_CACHE_ROM_SIZE is not a power of 2" 117 #endif 118 119 #define CACHE_ROM_BASE (((1 << 20) - (CONFIG_CACHE_ROM_SIZE >> 12)) << 12) 120 121 #endif 122