183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 270a09c6cSSimon Glass /* 370a09c6cSSimon Glass * Copyright (c) 2014 Google, Inc 470a09c6cSSimon Glass * 570a09c6cSSimon Glass * From Coreboot file of the same name 670a09c6cSSimon Glass */ 770a09c6cSSimon Glass 870a09c6cSSimon Glass #ifndef _ASM_MTRR_H 970a09c6cSSimon Glass #define _ASM_MTRR_H 1070a09c6cSSimon Glass 11aff2523fSSimon Glass /* MTRR region types */ 1270a09c6cSSimon Glass #define MTRR_TYPE_UNCACHEABLE 0 1370a09c6cSSimon Glass #define MTRR_TYPE_WRCOMB 1 1470a09c6cSSimon Glass #define MTRR_TYPE_WRTHROUGH 4 1570a09c6cSSimon Glass #define MTRR_TYPE_WRPROT 5 1670a09c6cSSimon Glass #define MTRR_TYPE_WRBACK 6 1770a09c6cSSimon Glass 18aff2523fSSimon Glass #define MTRR_TYPE_COUNT 7 1970a09c6cSSimon Glass 20aff2523fSSimon Glass #define MTRR_CAP_MSR 0x0fe 21aff2523fSSimon Glass #define MTRR_DEF_TYPE_MSR 0x2ff 2270a09c6cSSimon Glass 2343dd22f5SBin Meng #define MTRR_CAP_SMRR (1 << 11) 2443dd22f5SBin Meng #define MTRR_CAP_WC (1 << 10) 2543dd22f5SBin Meng #define MTRR_CAP_FIX (1 << 8) 2643dd22f5SBin Meng #define MTRR_CAP_VCNT_MASK 0xff 2743dd22f5SBin Meng 28aff2523fSSimon Glass #define MTRR_DEF_TYPE_EN (1 << 11) 29aff2523fSSimon Glass #define MTRR_DEF_TYPE_FIX_EN (1 << 10) 3070a09c6cSSimon Glass 31aff2523fSSimon Glass #define MTRR_PHYS_BASE_MSR(reg) (0x200 + 2 * (reg)) 32aff2523fSSimon Glass #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) 3370a09c6cSSimon Glass 34aff2523fSSimon Glass #define MTRR_PHYS_MASK_VALID (1 << 11) 3570a09c6cSSimon Glass 36aff2523fSSimon Glass #define MTRR_BASE_TYPE_MASK 0x7 37aff2523fSSimon Glass 38aff2523fSSimon Glass /* Number of MTRRs supported */ 39aff2523fSSimon Glass #define MTRR_COUNT 8 4070a09c6cSSimon Glass 4145b5a378SSimon Glass #define NUM_FIXED_MTRRS 11 421a06d2a3SSimon Glass #define RANGES_PER_FIXED_MTRR 8 4345b5a378SSimon Glass #define NUM_FIXED_RANGES (NUM_FIXED_MTRRS * RANGES_PER_FIXED_MTRR) 4445b5a378SSimon Glass 451a06d2a3SSimon Glass #define MTRR_FIX_64K_00000_MSR 0x250 461a06d2a3SSimon Glass #define MTRR_FIX_16K_80000_MSR 0x258 471a06d2a3SSimon Glass #define MTRR_FIX_16K_A0000_MSR 0x259 481a06d2a3SSimon Glass #define MTRR_FIX_4K_C0000_MSR 0x268 491a06d2a3SSimon Glass #define MTRR_FIX_4K_C8000_MSR 0x269 501a06d2a3SSimon Glass #define MTRR_FIX_4K_D0000_MSR 0x26a 511a06d2a3SSimon Glass #define MTRR_FIX_4K_D8000_MSR 0x26b 521a06d2a3SSimon Glass #define MTRR_FIX_4K_E0000_MSR 0x26c 531a06d2a3SSimon Glass #define MTRR_FIX_4K_E8000_MSR 0x26d 541a06d2a3SSimon Glass #define MTRR_FIX_4K_F0000_MSR 0x26e 551a06d2a3SSimon Glass #define MTRR_FIX_4K_F8000_MSR 0x26f 561a06d2a3SSimon Glass 578ba25eecSBin Meng #define MTRR_FIX_TYPE(t) ((t << 24) | (t << 16) | (t << 8) | t) 588ba25eecSBin Meng 5970a09c6cSSimon Glass #if !defined(__ASSEMBLER__) 6070a09c6cSSimon Glass 61aff2523fSSimon Glass /** 62aff2523fSSimon Glass * Information about the previous MTRR state, set up by mtrr_open() 63aff2523fSSimon Glass * 64aff2523fSSimon Glass * @deftype: Previous value of MTRR_DEF_TYPE_MSR 65aff2523fSSimon Glass * @enable_cache: true if cache was enabled 6670a09c6cSSimon Glass */ 67aff2523fSSimon Glass struct mtrr_state { 68aff2523fSSimon Glass uint64_t deftype; 69aff2523fSSimon Glass bool enable_cache; 70aff2523fSSimon Glass }; 71aff2523fSSimon Glass 72aff2523fSSimon Glass /** 73aff2523fSSimon Glass * mtrr_open() - Prepare to adjust MTRRs 74aff2523fSSimon Glass * 75aff2523fSSimon Glass * Use mtrr_open() passing in a structure - this function will init it. Then 76aff2523fSSimon Glass * when done, pass the same structure to mtrr_close() to re-enable MTRRs and 77aff2523fSSimon Glass * possibly the cache. 78aff2523fSSimon Glass * 79aff2523fSSimon Glass * @state: Empty structure to pass in to hold settings 80*590cee83SSimon Glass * @do_caches: true to disable caches before opening 8170a09c6cSSimon Glass */ 82*590cee83SSimon Glass void mtrr_open(struct mtrr_state *state, bool do_caches); 83aff2523fSSimon Glass 84aff2523fSSimon Glass /** 85aff2523fSSimon Glass * mtrr_open() - Clean up after adjusting MTRRs, and enable them 86aff2523fSSimon Glass * 87aff2523fSSimon Glass * This uses the structure containing information returned from mtrr_open(). 88aff2523fSSimon Glass * 89aff2523fSSimon Glass * @state: Structure from mtrr_open() 90*590cee83SSimon Glass * @state: true to restore cache state to that before mtrr_open() 91aff2523fSSimon Glass */ 92*590cee83SSimon Glass void mtrr_close(struct mtrr_state *state, bool do_caches); 93aff2523fSSimon Glass 94aff2523fSSimon Glass /** 95aff2523fSSimon Glass * mtrr_add_request() - Add a new MTRR request 96aff2523fSSimon Glass * 97aff2523fSSimon Glass * This adds a request for a memory region to be set up in a particular way. 98aff2523fSSimon Glass * 99aff2523fSSimon Glass * @type: Requested type (MTRR_TYPE_) 100aff2523fSSimon Glass * @start: Start address 101aff2523fSSimon Glass * @size: Size 1023b621ccaSBin Meng * 1033b621ccaSBin Meng * @return: 0 on success, non-zero on failure 104aff2523fSSimon Glass */ 105aff2523fSSimon Glass int mtrr_add_request(int type, uint64_t start, uint64_t size); 106aff2523fSSimon Glass 107aff2523fSSimon Glass /** 108aff2523fSSimon Glass * mtrr_commit() - set up the MTRR registers based on current requests 109aff2523fSSimon Glass * 110aff2523fSSimon Glass * This sets up MTRRs for the available DRAM and the requests received so far. 111aff2523fSSimon Glass * It must be called with caches disabled. 112aff2523fSSimon Glass * 113aff2523fSSimon Glass * @do_caches: true if caches are currently on 1143b621ccaSBin Meng * 1153b621ccaSBin Meng * @return: 0 on success, non-zero on failure 116aff2523fSSimon Glass */ 117aff2523fSSimon Glass int mtrr_commit(bool do_caches); 11870a09c6cSSimon Glass 11970a09c6cSSimon Glass #endif 12070a09c6cSSimon Glass 12170a09c6cSSimon Glass #if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0) 12270a09c6cSSimon Glass # error "CONFIG_XIP_ROM_SIZE is not a power of 2" 12370a09c6cSSimon Glass #endif 12470a09c6cSSimon Glass 12570a09c6cSSimon Glass #if ((CONFIG_CACHE_ROM_SIZE & (CONFIG_CACHE_ROM_SIZE - 1)) != 0) 12670a09c6cSSimon Glass # error "CONFIG_CACHE_ROM_SIZE is not a power of 2" 12770a09c6cSSimon Glass #endif 12870a09c6cSSimon Glass 12970a09c6cSSimon Glass #define CACHE_ROM_BASE (((1 << 20) - (CONFIG_CACHE_ROM_SIZE >> 12)) << 12) 13070a09c6cSSimon Glass 13170a09c6cSSimon Glass #endif 132