1*70a09c6cSSimon Glass /* 2*70a09c6cSSimon Glass * Copyright (c) 2014 Google, Inc 3*70a09c6cSSimon Glass * 4*70a09c6cSSimon Glass * From Coreboot file of the same name 5*70a09c6cSSimon Glass * 6*70a09c6cSSimon Glass * SPDX-License-Identifier: GPL-2.0+ 7*70a09c6cSSimon Glass */ 8*70a09c6cSSimon Glass 9*70a09c6cSSimon Glass #ifndef _ASM_MTRR_H 10*70a09c6cSSimon Glass #define _ASM_MTRR_H 11*70a09c6cSSimon Glass 12*70a09c6cSSimon Glass /* These are the region types */ 13*70a09c6cSSimon Glass #define MTRR_TYPE_UNCACHEABLE 0 14*70a09c6cSSimon Glass #define MTRR_TYPE_WRCOMB 1 15*70a09c6cSSimon Glass /*#define MTRR_TYPE_ 2*/ 16*70a09c6cSSimon Glass /*#define MTRR_TYPE_ 3*/ 17*70a09c6cSSimon Glass #define MTRR_TYPE_WRTHROUGH 4 18*70a09c6cSSimon Glass #define MTRR_TYPE_WRPROT 5 19*70a09c6cSSimon Glass #define MTRR_TYPE_WRBACK 6 20*70a09c6cSSimon Glass #define MTRR_NUM_TYPES 7 21*70a09c6cSSimon Glass 22*70a09c6cSSimon Glass #define MTRRcap_MSR 0x0fe 23*70a09c6cSSimon Glass #define MTRRdefType_MSR 0x2ff 24*70a09c6cSSimon Glass 25*70a09c6cSSimon Glass #define MTRRdefTypeEn (1 << 11) 26*70a09c6cSSimon Glass #define MTRRdefTypeFixEn (1 << 10) 27*70a09c6cSSimon Glass 28*70a09c6cSSimon Glass #define SMRRphysBase_MSR 0x1f2 29*70a09c6cSSimon Glass #define SMRRphysMask_MSR 0x1f3 30*70a09c6cSSimon Glass 31*70a09c6cSSimon Glass #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) 32*70a09c6cSSimon Glass #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) 33*70a09c6cSSimon Glass 34*70a09c6cSSimon Glass #define MTRRphysMaskValid (1 << 11) 35*70a09c6cSSimon Glass 36*70a09c6cSSimon Glass #define NUM_FIXED_RANGES 88 37*70a09c6cSSimon Glass #define RANGES_PER_FIXED_MTRR 8 38*70a09c6cSSimon Glass #define MTRRfix64K_00000_MSR 0x250 39*70a09c6cSSimon Glass #define MTRRfix16K_80000_MSR 0x258 40*70a09c6cSSimon Glass #define MTRRfix16K_A0000_MSR 0x259 41*70a09c6cSSimon Glass #define MTRRfix4K_C0000_MSR 0x268 42*70a09c6cSSimon Glass #define MTRRfix4K_C8000_MSR 0x269 43*70a09c6cSSimon Glass #define MTRRfix4K_D0000_MSR 0x26a 44*70a09c6cSSimon Glass #define MTRRfix4K_D8000_MSR 0x26b 45*70a09c6cSSimon Glass #define MTRRfix4K_E0000_MSR 0x26c 46*70a09c6cSSimon Glass #define MTRRfix4K_E8000_MSR 0x26d 47*70a09c6cSSimon Glass #define MTRRfix4K_F0000_MSR 0x26e 48*70a09c6cSSimon Glass #define MTRRfix4K_F8000_MSR 0x26f 49*70a09c6cSSimon Glass 50*70a09c6cSSimon Glass #if !defined(__ASSEMBLER__) 51*70a09c6cSSimon Glass 52*70a09c6cSSimon Glass /* 53*70a09c6cSSimon Glass * The MTRR code has some side effects that the callers should be aware for. 54*70a09c6cSSimon Glass * 1. The call sequence matters. x86_setup_mtrrs() calls 55*70a09c6cSSimon Glass * x86_setup_fixed_mtrrs_no_enable() then enable_fixed_mtrrs() (equivalent 56*70a09c6cSSimon Glass * of x86_setup_fixed_mtrrs()) then x86_setup_var_mtrrs(). If the callers 57*70a09c6cSSimon Glass * want to call the components of x86_setup_mtrrs() because of other 58*70a09c6cSSimon Glass * rquirements the ordering should still preserved. 59*70a09c6cSSimon Glass * 2. enable_fixed_mtrr() will enable both variable and fixed MTRRs because 60*70a09c6cSSimon Glass * of the nature of the global MTRR enable flag. Therefore, all direct 61*70a09c6cSSimon Glass * or indirect callers of enable_fixed_mtrr() should ensure that the 62*70a09c6cSSimon Glass * variable MTRR MSRs do not contain bad ranges. 63*70a09c6cSSimon Glass * 3. If CONFIG_CACHE_ROM is selected an MTRR is allocated for enabling 64*70a09c6cSSimon Glass * the caching of the ROM. However, it is set to uncacheable (UC). It 65*70a09c6cSSimon Glass * is the responsiblity of the caller to enable it by calling 66*70a09c6cSSimon Glass * x86_mtrr_enable_rom_caching(). 67*70a09c6cSSimon Glass */ 68*70a09c6cSSimon Glass void x86_setup_mtrrs(void); 69*70a09c6cSSimon Glass /* 70*70a09c6cSSimon Glass * x86_setup_var_mtrrs() parameters: 71*70a09c6cSSimon Glass * address_bits - number of physical address bits supported by cpu 72*70a09c6cSSimon Glass * above4gb - 2 means dynamically detect number of variable MTRRs available. 73*70a09c6cSSimon Glass * non-zero means handle memory ranges above 4GiB. 74*70a09c6cSSimon Glass * 0 means ignore memory ranges above 4GiB 75*70a09c6cSSimon Glass */ 76*70a09c6cSSimon Glass void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb); 77*70a09c6cSSimon Glass void enable_fixed_mtrr(void); 78*70a09c6cSSimon Glass void x86_setup_fixed_mtrrs(void); 79*70a09c6cSSimon Glass /* Set up fixed MTRRs but do not enable them. */ 80*70a09c6cSSimon Glass void x86_setup_fixed_mtrrs_no_enable(void); 81*70a09c6cSSimon Glass int x86_mtrr_check(void); 82*70a09c6cSSimon Glass /* ROM caching can be used after variable MTRRs are set up. Beware that 83*70a09c6cSSimon Glass * enabling CONFIG_CACHE_ROM will eat through quite a few MTRRs based on 84*70a09c6cSSimon Glass * one's IO hole size and WRCOMB resources. Be sure to check the console 85*70a09c6cSSimon Glass * log when enabling CONFIG_CACHE_ROM or adding WRCOMB resources. Beware that 86*70a09c6cSSimon Glass * on CPUs with core-scoped MTRR registers such as hyperthreaded CPUs the 87*70a09c6cSSimon Glass * rom caching will be disabled if all threads run the MTRR code. Therefore, 88*70a09c6cSSimon Glass * one needs to call x86_mtrr_enable_rom_caching() after all threads of the 89*70a09c6cSSimon Glass * same core have run the MTRR code. */ 90*70a09c6cSSimon Glass #if CONFIG_CACHE_ROM 91*70a09c6cSSimon Glass void x86_mtrr_enable_rom_caching(void); 92*70a09c6cSSimon Glass void x86_mtrr_disable_rom_caching(void); 93*70a09c6cSSimon Glass /* Return the variable range MTRR index of the ROM cache. */ 94*70a09c6cSSimon Glass long x86_mtrr_rom_cache_var_index(void); 95*70a09c6cSSimon Glass #else 96*70a09c6cSSimon Glass static inline void x86_mtrr_enable_rom_caching(void) {} 97*70a09c6cSSimon Glass static inline void x86_mtrr_disable_rom_caching(void) {} 98*70a09c6cSSimon Glass static inline long x86_mtrr_rom_cache_var_index(void) { return -1; } 99*70a09c6cSSimon Glass #endif /* CONFIG_CACHE_ROM */ 100*70a09c6cSSimon Glass 101*70a09c6cSSimon Glass #endif 102*70a09c6cSSimon Glass 103*70a09c6cSSimon Glass #if !defined(CONFIG_RAMTOP) 104*70a09c6cSSimon Glass # error "CONFIG_RAMTOP not defined" 105*70a09c6cSSimon Glass #endif 106*70a09c6cSSimon Glass 107*70a09c6cSSimon Glass #if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0) 108*70a09c6cSSimon Glass # error "CONFIG_XIP_ROM_SIZE is not a power of 2" 109*70a09c6cSSimon Glass #endif 110*70a09c6cSSimon Glass 111*70a09c6cSSimon Glass #if ((CONFIG_CACHE_ROM_SIZE & (CONFIG_CACHE_ROM_SIZE - 1)) != 0) 112*70a09c6cSSimon Glass # error "CONFIG_CACHE_ROM_SIZE is not a power of 2" 113*70a09c6cSSimon Glass #endif 114*70a09c6cSSimon Glass 115*70a09c6cSSimon Glass #define CACHE_ROM_BASE (((1 << 20) - (CONFIG_CACHE_ROM_SIZE >> 12)) << 12) 116*70a09c6cSSimon Glass 117*70a09c6cSSimon Glass #if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0 118*70a09c6cSSimon Glass # error "CONFIG_RAMTOP must be a power of 2" 119*70a09c6cSSimon Glass #endif 120*70a09c6cSSimon Glass 121*70a09c6cSSimon Glass #endif 122