170a09c6cSSimon Glass /* 270a09c6cSSimon Glass * Copyright (c) 2014 Google, Inc 370a09c6cSSimon Glass * 470a09c6cSSimon Glass * From Coreboot file of the same name 570a09c6cSSimon Glass * 670a09c6cSSimon Glass * SPDX-License-Identifier: GPL-2.0+ 770a09c6cSSimon Glass */ 870a09c6cSSimon Glass 970a09c6cSSimon Glass #ifndef _ASM_MTRR_H 1070a09c6cSSimon Glass #define _ASM_MTRR_H 1170a09c6cSSimon Glass 12aff2523fSSimon Glass /* MTRR region types */ 1370a09c6cSSimon Glass #define MTRR_TYPE_UNCACHEABLE 0 1470a09c6cSSimon Glass #define MTRR_TYPE_WRCOMB 1 1570a09c6cSSimon Glass #define MTRR_TYPE_WRTHROUGH 4 1670a09c6cSSimon Glass #define MTRR_TYPE_WRPROT 5 1770a09c6cSSimon Glass #define MTRR_TYPE_WRBACK 6 1870a09c6cSSimon Glass 19aff2523fSSimon Glass #define MTRR_TYPE_COUNT 7 2070a09c6cSSimon Glass 21aff2523fSSimon Glass #define MTRR_CAP_MSR 0x0fe 22aff2523fSSimon Glass #define MTRR_DEF_TYPE_MSR 0x2ff 2370a09c6cSSimon Glass 24*43dd22f5SBin Meng #define MTRR_CAP_SMRR (1 << 11) 25*43dd22f5SBin Meng #define MTRR_CAP_WC (1 << 10) 26*43dd22f5SBin Meng #define MTRR_CAP_FIX (1 << 8) 27*43dd22f5SBin Meng #define MTRR_CAP_VCNT_MASK 0xff 28*43dd22f5SBin Meng 29aff2523fSSimon Glass #define MTRR_DEF_TYPE_EN (1 << 11) 30aff2523fSSimon Glass #define MTRR_DEF_TYPE_FIX_EN (1 << 10) 3170a09c6cSSimon Glass 32aff2523fSSimon Glass #define MTRR_PHYS_BASE_MSR(reg) (0x200 + 2 * (reg)) 33aff2523fSSimon Glass #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) 3470a09c6cSSimon Glass 35aff2523fSSimon Glass #define MTRR_PHYS_MASK_VALID (1 << 11) 3670a09c6cSSimon Glass 37aff2523fSSimon Glass #define MTRR_BASE_TYPE_MASK 0x7 38aff2523fSSimon Glass 39aff2523fSSimon Glass /* Number of MTRRs supported */ 40aff2523fSSimon Glass #define MTRR_COUNT 8 4170a09c6cSSimon Glass 4245b5a378SSimon Glass #define NUM_FIXED_MTRRS 11 431a06d2a3SSimon Glass #define RANGES_PER_FIXED_MTRR 8 4445b5a378SSimon Glass #define NUM_FIXED_RANGES (NUM_FIXED_MTRRS * RANGES_PER_FIXED_MTRR) 4545b5a378SSimon Glass 461a06d2a3SSimon Glass #define MTRR_FIX_64K_00000_MSR 0x250 471a06d2a3SSimon Glass #define MTRR_FIX_16K_80000_MSR 0x258 481a06d2a3SSimon Glass #define MTRR_FIX_16K_A0000_MSR 0x259 491a06d2a3SSimon Glass #define MTRR_FIX_4K_C0000_MSR 0x268 501a06d2a3SSimon Glass #define MTRR_FIX_4K_C8000_MSR 0x269 511a06d2a3SSimon Glass #define MTRR_FIX_4K_D0000_MSR 0x26a 521a06d2a3SSimon Glass #define MTRR_FIX_4K_D8000_MSR 0x26b 531a06d2a3SSimon Glass #define MTRR_FIX_4K_E0000_MSR 0x26c 541a06d2a3SSimon Glass #define MTRR_FIX_4K_E8000_MSR 0x26d 551a06d2a3SSimon Glass #define MTRR_FIX_4K_F0000_MSR 0x26e 561a06d2a3SSimon Glass #define MTRR_FIX_4K_F8000_MSR 0x26f 571a06d2a3SSimon Glass 5870a09c6cSSimon Glass #if !defined(__ASSEMBLER__) 5970a09c6cSSimon Glass 60aff2523fSSimon Glass /** 61aff2523fSSimon Glass * Information about the previous MTRR state, set up by mtrr_open() 62aff2523fSSimon Glass * 63aff2523fSSimon Glass * @deftype: Previous value of MTRR_DEF_TYPE_MSR 64aff2523fSSimon Glass * @enable_cache: true if cache was enabled 6570a09c6cSSimon Glass */ 66aff2523fSSimon Glass struct mtrr_state { 67aff2523fSSimon Glass uint64_t deftype; 68aff2523fSSimon Glass bool enable_cache; 69aff2523fSSimon Glass }; 70aff2523fSSimon Glass 71aff2523fSSimon Glass /** 72aff2523fSSimon Glass * mtrr_open() - Prepare to adjust MTRRs 73aff2523fSSimon Glass * 74aff2523fSSimon Glass * Use mtrr_open() passing in a structure - this function will init it. Then 75aff2523fSSimon Glass * when done, pass the same structure to mtrr_close() to re-enable MTRRs and 76aff2523fSSimon Glass * possibly the cache. 77aff2523fSSimon Glass * 78aff2523fSSimon Glass * @state: Empty structure to pass in to hold settings 7970a09c6cSSimon Glass */ 80aff2523fSSimon Glass void mtrr_open(struct mtrr_state *state); 81aff2523fSSimon Glass 82aff2523fSSimon Glass /** 83aff2523fSSimon Glass * mtrr_open() - Clean up after adjusting MTRRs, and enable them 84aff2523fSSimon Glass * 85aff2523fSSimon Glass * This uses the structure containing information returned from mtrr_open(). 86aff2523fSSimon Glass * 87aff2523fSSimon Glass * @state: Structure from mtrr_open() 88aff2523fSSimon Glass */ 89aff2523fSSimon Glass void mtrr_close(struct mtrr_state *state); 90aff2523fSSimon Glass 91aff2523fSSimon Glass /** 92aff2523fSSimon Glass * mtrr_add_request() - Add a new MTRR request 93aff2523fSSimon Glass * 94aff2523fSSimon Glass * This adds a request for a memory region to be set up in a particular way. 95aff2523fSSimon Glass * 96aff2523fSSimon Glass * @type: Requested type (MTRR_TYPE_) 97aff2523fSSimon Glass * @start: Start address 98aff2523fSSimon Glass * @size: Size 993b621ccaSBin Meng * 1003b621ccaSBin Meng * @return: 0 on success, non-zero on failure 101aff2523fSSimon Glass */ 102aff2523fSSimon Glass int mtrr_add_request(int type, uint64_t start, uint64_t size); 103aff2523fSSimon Glass 104aff2523fSSimon Glass /** 105aff2523fSSimon Glass * mtrr_commit() - set up the MTRR registers based on current requests 106aff2523fSSimon Glass * 107aff2523fSSimon Glass * This sets up MTRRs for the available DRAM and the requests received so far. 108aff2523fSSimon Glass * It must be called with caches disabled. 109aff2523fSSimon Glass * 110aff2523fSSimon Glass * @do_caches: true if caches are currently on 1113b621ccaSBin Meng * 1123b621ccaSBin Meng * @return: 0 on success, non-zero on failure 113aff2523fSSimon Glass */ 114aff2523fSSimon Glass int mtrr_commit(bool do_caches); 11570a09c6cSSimon Glass 11670a09c6cSSimon Glass #endif 11770a09c6cSSimon Glass 11870a09c6cSSimon Glass #if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0) 11970a09c6cSSimon Glass # error "CONFIG_XIP_ROM_SIZE is not a power of 2" 12070a09c6cSSimon Glass #endif 12170a09c6cSSimon Glass 12270a09c6cSSimon Glass #if ((CONFIG_CACHE_ROM_SIZE & (CONFIG_CACHE_ROM_SIZE - 1)) != 0) 12370a09c6cSSimon Glass # error "CONFIG_CACHE_ROM_SIZE is not a power of 2" 12470a09c6cSSimon Glass #endif 12570a09c6cSSimon Glass 12670a09c6cSSimon Glass #define CACHE_ROM_BASE (((1 << 20) - (CONFIG_CACHE_ROM_SIZE >> 12)) << 12) 12770a09c6cSSimon Glass 12870a09c6cSSimon Glass #endif 129