170a09c6cSSimon Glass /* 270a09c6cSSimon Glass * Copyright (c) 2014 Google, Inc 370a09c6cSSimon Glass * 470a09c6cSSimon Glass * From Coreboot file of the same name 570a09c6cSSimon Glass * 670a09c6cSSimon Glass * SPDX-License-Identifier: GPL-2.0+ 770a09c6cSSimon Glass */ 870a09c6cSSimon Glass 970a09c6cSSimon Glass #ifndef _ASM_MTRR_H 1070a09c6cSSimon Glass #define _ASM_MTRR_H 1170a09c6cSSimon Glass 12aff2523fSSimon Glass /* MTRR region types */ 1370a09c6cSSimon Glass #define MTRR_TYPE_UNCACHEABLE 0 1470a09c6cSSimon Glass #define MTRR_TYPE_WRCOMB 1 1570a09c6cSSimon Glass #define MTRR_TYPE_WRTHROUGH 4 1670a09c6cSSimon Glass #define MTRR_TYPE_WRPROT 5 1770a09c6cSSimon Glass #define MTRR_TYPE_WRBACK 6 1870a09c6cSSimon Glass 19aff2523fSSimon Glass #define MTRR_TYPE_COUNT 7 2070a09c6cSSimon Glass 21aff2523fSSimon Glass #define MTRR_CAP_MSR 0x0fe 22aff2523fSSimon Glass #define MTRR_DEF_TYPE_MSR 0x2ff 2370a09c6cSSimon Glass 24aff2523fSSimon Glass #define MTRR_DEF_TYPE_EN (1 << 11) 25aff2523fSSimon Glass #define MTRR_DEF_TYPE_FIX_EN (1 << 10) 2670a09c6cSSimon Glass 27aff2523fSSimon Glass #define MTRR_PHYS_BASE_MSR(reg) (0x200 + 2 * (reg)) 28aff2523fSSimon Glass #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1) 2970a09c6cSSimon Glass 30aff2523fSSimon Glass #define MTRR_PHYS_MASK_VALID (1 << 11) 3170a09c6cSSimon Glass 32aff2523fSSimon Glass #define MTRR_BASE_TYPE_MASK 0x7 33aff2523fSSimon Glass 34aff2523fSSimon Glass /* Number of MTRRs supported */ 35aff2523fSSimon Glass #define MTRR_COUNT 8 3670a09c6cSSimon Glass 3770a09c6cSSimon Glass #if !defined(__ASSEMBLER__) 3870a09c6cSSimon Glass 39aff2523fSSimon Glass /** 40aff2523fSSimon Glass * Information about the previous MTRR state, set up by mtrr_open() 41aff2523fSSimon Glass * 42aff2523fSSimon Glass * @deftype: Previous value of MTRR_DEF_TYPE_MSR 43aff2523fSSimon Glass * @enable_cache: true if cache was enabled 4470a09c6cSSimon Glass */ 45aff2523fSSimon Glass struct mtrr_state { 46aff2523fSSimon Glass uint64_t deftype; 47aff2523fSSimon Glass bool enable_cache; 48aff2523fSSimon Glass }; 49aff2523fSSimon Glass 50aff2523fSSimon Glass /** 51aff2523fSSimon Glass * mtrr_open() - Prepare to adjust MTRRs 52aff2523fSSimon Glass * 53aff2523fSSimon Glass * Use mtrr_open() passing in a structure - this function will init it. Then 54aff2523fSSimon Glass * when done, pass the same structure to mtrr_close() to re-enable MTRRs and 55aff2523fSSimon Glass * possibly the cache. 56aff2523fSSimon Glass * 57aff2523fSSimon Glass * @state: Empty structure to pass in to hold settings 5870a09c6cSSimon Glass */ 59aff2523fSSimon Glass void mtrr_open(struct mtrr_state *state); 60aff2523fSSimon Glass 61aff2523fSSimon Glass /** 62aff2523fSSimon Glass * mtrr_open() - Clean up after adjusting MTRRs, and enable them 63aff2523fSSimon Glass * 64aff2523fSSimon Glass * This uses the structure containing information returned from mtrr_open(). 65aff2523fSSimon Glass * 66aff2523fSSimon Glass * @state: Structure from mtrr_open() 67aff2523fSSimon Glass */ 68aff2523fSSimon Glass void mtrr_close(struct mtrr_state *state); 69aff2523fSSimon Glass 70aff2523fSSimon Glass /** 71aff2523fSSimon Glass * mtrr_add_request() - Add a new MTRR request 72aff2523fSSimon Glass * 73aff2523fSSimon Glass * This adds a request for a memory region to be set up in a particular way. 74aff2523fSSimon Glass * 75aff2523fSSimon Glass * @type: Requested type (MTRR_TYPE_) 76aff2523fSSimon Glass * @start: Start address 77aff2523fSSimon Glass * @size: Size 78*3b621ccaSBin Meng * 79*3b621ccaSBin Meng * @return: 0 on success, non-zero on failure 80aff2523fSSimon Glass */ 81aff2523fSSimon Glass int mtrr_add_request(int type, uint64_t start, uint64_t size); 82aff2523fSSimon Glass 83aff2523fSSimon Glass /** 84aff2523fSSimon Glass * mtrr_commit() - set up the MTRR registers based on current requests 85aff2523fSSimon Glass * 86aff2523fSSimon Glass * This sets up MTRRs for the available DRAM and the requests received so far. 87aff2523fSSimon Glass * It must be called with caches disabled. 88aff2523fSSimon Glass * 89aff2523fSSimon Glass * @do_caches: true if caches are currently on 90*3b621ccaSBin Meng * 91*3b621ccaSBin Meng * @return: 0 on success, non-zero on failure 92aff2523fSSimon Glass */ 93aff2523fSSimon Glass int mtrr_commit(bool do_caches); 9470a09c6cSSimon Glass 9570a09c6cSSimon Glass #endif 9670a09c6cSSimon Glass 9770a09c6cSSimon Glass #if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0) 9870a09c6cSSimon Glass # error "CONFIG_XIP_ROM_SIZE is not a power of 2" 9970a09c6cSSimon Glass #endif 10070a09c6cSSimon Glass 10170a09c6cSSimon Glass #if ((CONFIG_CACHE_ROM_SIZE & (CONFIG_CACHE_ROM_SIZE - 1)) != 0) 10270a09c6cSSimon Glass # error "CONFIG_CACHE_ROM_SIZE is not a power of 2" 10370a09c6cSSimon Glass #endif 10470a09c6cSSimon Glass 10570a09c6cSSimon Glass #define CACHE_ROM_BASE (((1 << 20) - (CONFIG_CACHE_ROM_SIZE >> 12)) << 12) 10670a09c6cSSimon Glass 10770a09c6cSSimon Glass #endif 108