1 /* 2 * Taken from the linux kernel file of the same name 3 * 4 * (C) Copyright 2012 5 * Graeme Russ, <graeme.russ@gmail.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef _ASM_X86_MSR_H 24 #define _ASM_X86_MSR_H 25 26 #include <asm/msr-index.h> 27 28 #ifndef __ASSEMBLY__ 29 30 #include <linux/types.h> 31 #include <linux/ioctl.h> 32 33 #define X86_IOC_RDMSR_REGS _IOWR('c', 0xA0, __u32[8]) 34 #define X86_IOC_WRMSR_REGS _IOWR('c', 0xA1, __u32[8]) 35 36 #ifdef __KERNEL__ 37 38 #include <asm/errno.h> 39 40 struct msr { 41 union { 42 struct { 43 u32 l; 44 u32 h; 45 }; 46 u64 q; 47 }; 48 }; 49 50 struct msr_info { 51 u32 msr_no; 52 struct msr reg; 53 struct msr *msrs; 54 int err; 55 }; 56 57 struct msr_regs_info { 58 u32 *regs; 59 int err; 60 }; 61 62 static inline unsigned long long native_read_tscp(unsigned int *aux) 63 { 64 unsigned long low, high; 65 asm volatile(".byte 0x0f,0x01,0xf9" 66 : "=a" (low), "=d" (high), "=c" (*aux)); 67 return low | ((u64)high << 32); 68 } 69 70 /* 71 * both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A" 72 * constraint has different meanings. For i386, "A" means exactly 73 * edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead, 74 * it means rax *or* rdx. 75 */ 76 #ifdef CONFIG_X86_64 77 #define DECLARE_ARGS(val, low, high) unsigned low, high 78 #define EAX_EDX_VAL(val, low, high) ((low) | ((u64)(high) << 32)) 79 #define EAX_EDX_ARGS(val, low, high) "a" (low), "d" (high) 80 #define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high) 81 #else 82 #define DECLARE_ARGS(val, low, high) unsigned long long val 83 #define EAX_EDX_VAL(val, low, high) (val) 84 #define EAX_EDX_ARGS(val, low, high) "A" (val) 85 #define EAX_EDX_RET(val, low, high) "=A" (val) 86 #endif 87 88 static inline __attribute__((no_instrument_function)) 89 unsigned long long native_read_msr(unsigned int msr) 90 { 91 DECLARE_ARGS(val, low, high); 92 93 asm volatile("rdmsr" : EAX_EDX_RET(val, low, high) : "c" (msr)); 94 return EAX_EDX_VAL(val, low, high); 95 } 96 97 static inline void native_write_msr(unsigned int msr, 98 unsigned low, unsigned high) 99 { 100 asm volatile("wrmsr" : : "c" (msr), "a"(low), "d" (high) : "memory"); 101 } 102 103 extern unsigned long long native_read_tsc(void); 104 105 extern int native_rdmsr_safe_regs(u32 regs[8]); 106 extern int native_wrmsr_safe_regs(u32 regs[8]); 107 108 static inline unsigned long long native_read_pmc(int counter) 109 { 110 DECLARE_ARGS(val, low, high); 111 112 asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter)); 113 return EAX_EDX_VAL(val, low, high); 114 } 115 116 #ifdef CONFIG_PARAVIRT 117 #include <asm/paravirt.h> 118 #else 119 #include <errno.h> 120 /* 121 * Access to machine-specific registers (available on 586 and better only) 122 * Note: the rd* operations modify the parameters directly (without using 123 * pointer indirection), this allows gcc to optimize better 124 */ 125 126 #define rdmsr(msr, val1, val2) \ 127 do { \ 128 u64 __val = native_read_msr((msr)); \ 129 (void)((val1) = (u32)__val); \ 130 (void)((val2) = (u32)(__val >> 32)); \ 131 } while (0) 132 133 static inline void wrmsr(unsigned msr, unsigned low, unsigned high) 134 { 135 native_write_msr(msr, low, high); 136 } 137 138 #define rdmsrl(msr, val) \ 139 ((val) = native_read_msr((msr))) 140 141 #define wrmsrl(msr, val) \ 142 native_write_msr((msr), (u32)((u64)(val)), (u32)((u64)(val) >> 32)) 143 144 /* rdmsr with exception handling */ 145 #define rdmsr_safe(msr, p1, p2) \ 146 ({ \ 147 int __err; \ 148 u64 __val = native_read_msr_safe((msr), &__err); \ 149 (*p1) = (u32)__val; \ 150 (*p2) = (u32)(__val >> 32); \ 151 __err; \ 152 }) 153 154 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) 155 { 156 u32 gprs[8] = { 0 }; 157 int err; 158 159 gprs[1] = msr; 160 gprs[7] = 0x9c5a203a; 161 162 err = native_rdmsr_safe_regs(gprs); 163 164 *p = gprs[0] | ((u64)gprs[2] << 32); 165 166 return err; 167 } 168 169 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val) 170 { 171 u32 gprs[8] = { 0 }; 172 173 gprs[0] = (u32)val; 174 gprs[1] = msr; 175 gprs[2] = val >> 32; 176 gprs[7] = 0x9c5a203a; 177 178 return native_wrmsr_safe_regs(gprs); 179 } 180 181 static inline int rdmsr_safe_regs(u32 regs[8]) 182 { 183 return native_rdmsr_safe_regs(regs); 184 } 185 186 static inline int wrmsr_safe_regs(u32 regs[8]) 187 { 188 return native_wrmsr_safe_regs(regs); 189 } 190 191 #define rdtscl(low) \ 192 ((low) = (u32)__native_read_tsc()) 193 194 #define rdtscll(val) \ 195 ((val) = __native_read_tsc()) 196 197 #define rdpmc(counter, low, high) \ 198 do { \ 199 u64 _l = native_read_pmc((counter)); \ 200 (low) = (u32)_l; \ 201 (high) = (u32)(_l >> 32); \ 202 } while (0) 203 204 #define rdtscp(low, high, aux) \ 205 do { \ 206 unsigned long long _val = native_read_tscp(&(aux)); \ 207 (low) = (u32)_val; \ 208 (high) = (u32)(_val >> 32); \ 209 } while (0) 210 211 #define rdtscpll(val, aux) (val) = native_read_tscp(&(aux)) 212 213 #endif /* !CONFIG_PARAVIRT */ 214 215 216 #define checking_wrmsrl(msr, val) wrmsr_safe((msr), (u32)(val), \ 217 (u32)((val) >> 32)) 218 219 #define write_tsc(val1, val2) wrmsr(MSR_IA32_TSC, (val1), (val2)) 220 221 #define write_rdtscp_aux(val) wrmsr(MSR_TSC_AUX, (val), 0) 222 223 struct msr *msrs_alloc(void); 224 void msrs_free(struct msr *msrs); 225 226 #ifdef CONFIG_SMP 227 int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); 228 int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); 229 void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); 230 void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); 231 int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); 232 int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); 233 int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); 234 int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); 235 236 #endif /* CONFIG_SMP */ 237 #endif /* __KERNEL__ */ 238 #endif /* __ASSEMBLY__ */ 239 #endif /* _ASM_X86_MSR_H */ 240