1 /* 2 * Taken from the linux kernel file of the same name 3 * 4 * (C) Copyright 2012 5 * Graeme Russ, <graeme.russ@gmail.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _ASM_X86_MSR_INDEX_H 11 #define _ASM_X86_MSR_INDEX_H 12 13 /* CPU model specific register (MSR) numbers */ 14 15 /* x86-64 specific MSRs */ 16 #define MSR_EFER 0xc0000080 /* extended feature register */ 17 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 18 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 19 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 20 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 21 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 22 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 23 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 24 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 25 26 /* EFER bits: */ 27 #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 28 #define _EFER_LME 8 /* Long mode enable */ 29 #define _EFER_LMA 10 /* Long mode active (read-only) */ 30 #define _EFER_NX 11 /* No execute enable */ 31 #define _EFER_SVME 12 /* Enable virtualization */ 32 #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 33 #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 34 35 #define EFER_SCE (1<<_EFER_SCE) 36 #define EFER_LME (1<<_EFER_LME) 37 #define EFER_LMA (1<<_EFER_LMA) 38 #define EFER_NX (1<<_EFER_NX) 39 #define EFER_SVME (1<<_EFER_SVME) 40 #define EFER_LMSLE (1<<_EFER_LMSLE) 41 #define EFER_FFXSR (1<<_EFER_FFXSR) 42 43 /* Intel MSRs. Some also available on other CPUs */ 44 #define MSR_IA32_PERFCTR0 0x000000c1 45 #define MSR_IA32_PERFCTR1 0x000000c2 46 #define MSR_FSB_FREQ 0x000000cd 47 #define MSR_NHM_PLATFORM_INFO 0x000000ce 48 49 #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 50 #define NHM_C3_AUTO_DEMOTE (1UL << 25) 51 #define NHM_C1_AUTO_DEMOTE (1UL << 26) 52 #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 53 #define SNB_C1_AUTO_UNDEMOTE (1UL << 27) 54 #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) 55 56 #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0x000000cd 57 #define MSR_PLATFORM_INFO 0x000000ce 58 #define MSR_PMG_CST_CONFIG_CONTROL 0x000000e2 59 #define SINGLE_PCTL (1 << 11) 60 61 #define MSR_MTRRcap 0x000000fe 62 #define MSR_IA32_BBL_CR_CTL 0x00000119 63 #define MSR_IA32_BBL_CR_CTL3 0x0000011e 64 #define MSR_POWER_MISC 0x00000120 65 #define ENABLE_ULFM_AUTOCM_MASK (1 << 2) 66 #define ENABLE_INDP_AUTOCM_MASK (1 << 3) 67 68 #define MSR_IA32_SYSENTER_CS 0x00000174 69 #define MSR_IA32_SYSENTER_ESP 0x00000175 70 #define MSR_IA32_SYSENTER_EIP 0x00000176 71 72 #define MSR_IA32_MCG_CAP 0x00000179 73 #define MSR_IA32_MCG_STATUS 0x0000017a 74 #define MSR_IA32_MCG_CTL 0x0000017b 75 76 #define MSR_IA32_MISC_ENABLES 0x000001a0 77 #define MSR_OFFCORE_RSP_0 0x000001a6 78 #define MSR_OFFCORE_RSP_1 0x000001a7 79 #define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad 80 #define MSR_IVT_TURBO_RATIO_LIMIT 0x000001ae 81 82 #define MSR_LBR_SELECT 0x000001c8 83 #define MSR_LBR_TOS 0x000001c9 84 #define MSR_POWER_CTL 0x000001fc 85 #define MSR_LBR_NHM_FROM 0x00000680 86 #define MSR_LBR_NHM_TO 0x000006c0 87 #define MSR_LBR_CORE_FROM 0x00000040 88 #define MSR_LBR_CORE_TO 0x00000060 89 90 #define MSR_IA32_PEBS_ENABLE 0x000003f1 91 #define MSR_IA32_DS_AREA 0x00000600 92 #define MSR_IA32_PERF_CAPABILITIES 0x00000345 93 #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 94 95 #define MSR_MTRRfix64K_00000 0x00000250 96 #define MSR_MTRRfix16K_80000 0x00000258 97 #define MSR_MTRRfix16K_A0000 0x00000259 98 #define MSR_MTRRfix4K_C0000 0x00000268 99 #define MSR_MTRRfix4K_C8000 0x00000269 100 #define MSR_MTRRfix4K_D0000 0x0000026a 101 #define MSR_MTRRfix4K_D8000 0x0000026b 102 #define MSR_MTRRfix4K_E0000 0x0000026c 103 #define MSR_MTRRfix4K_E8000 0x0000026d 104 #define MSR_MTRRfix4K_F0000 0x0000026e 105 #define MSR_MTRRfix4K_F8000 0x0000026f 106 #define MSR_MTRRdefType 0x000002ff 107 108 #define MSR_IA32_CR_PAT 0x00000277 109 110 #define MSR_IA32_DEBUGCTLMSR 0x000001d9 111 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 112 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 113 #define MSR_IA32_LASTINTFROMIP 0x000001dd 114 #define MSR_IA32_LASTINTTOIP 0x000001de 115 116 /* DEBUGCTLMSR bits (others vary by model): */ 117 #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 118 /* single-step on branches */ 119 #define DEBUGCTLMSR_BTF (1UL << 1) 120 #define DEBUGCTLMSR_TR (1UL << 6) 121 #define DEBUGCTLMSR_BTS (1UL << 7) 122 #define DEBUGCTLMSR_BTINT (1UL << 8) 123 #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 124 #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 125 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 126 127 #define MSR_IA32_POWER_CTL 0x000001fc 128 129 #define MSR_IA32_MC0_CTL 0x00000400 130 #define MSR_IA32_MC0_STATUS 0x00000401 131 #define MSR_IA32_MC0_ADDR 0x00000402 132 #define MSR_IA32_MC0_MISC 0x00000403 133 134 /* C-state Residency Counters */ 135 #define MSR_PKG_C3_RESIDENCY 0x000003f8 136 #define MSR_PKG_C6_RESIDENCY 0x000003f9 137 #define MSR_PKG_C7_RESIDENCY 0x000003fa 138 #define MSR_CORE_C3_RESIDENCY 0x000003fc 139 #define MSR_CORE_C6_RESIDENCY 0x000003fd 140 #define MSR_CORE_C7_RESIDENCY 0x000003fe 141 #define MSR_PKG_C2_RESIDENCY 0x0000060d 142 #define MSR_PKG_C8_RESIDENCY 0x00000630 143 #define MSR_PKG_C9_RESIDENCY 0x00000631 144 #define MSR_PKG_C10_RESIDENCY 0x00000632 145 146 /* Run Time Average Power Limiting (RAPL) Interface */ 147 148 #define MSR_PKG_POWER_SKU_UNIT 0x00000606 149 150 #define MSR_PKG_POWER_LIMIT 0x00000610 151 #define MSR_PKG_ENERGY_STATUS 0x00000611 152 #define MSR_PKG_PERF_STATUS 0x00000613 153 #define MSR_PKG_POWER_INFO 0x00000614 154 155 #define MSR_DRAM_POWER_LIMIT 0x00000618 156 #define MSR_DRAM_ENERGY_STATUS 0x00000619 157 #define MSR_DRAM_PERF_STATUS 0x0000061b 158 #define MSR_DRAM_POWER_INFO 0x0000061c 159 160 #define MSR_PP0_POWER_LIMIT 0x00000638 161 #define MSR_PP0_ENERGY_STATUS 0x00000639 162 #define MSR_PP0_POLICY 0x0000063a 163 #define MSR_PP0_PERF_STATUS 0x0000063b 164 165 #define MSR_PP1_POWER_LIMIT 0x00000640 166 #define MSR_PP1_ENERGY_STATUS 0x00000641 167 #define MSR_PP1_POLICY 0x00000642 168 169 #define MSR_CORE_C1_RES 0x00000660 170 #define MSR_IACORE_RATIOS 0x0000066a 171 #define MSR_IACORE_TURBO_RATIOS 0x0000066c 172 #define MSR_IACORE_VIDS 0x0000066b 173 #define MSR_IACORE_TURBO_VIDS 0x0000066d 174 #define MSR_PKG_TURBO_CFG1 0x00000670 175 #define MSR_CPU_TURBO_WKLD_CFG1 0x00000671 176 #define MSR_CPU_TURBO_WKLD_CFG2 0x00000672 177 #define MSR_CPU_THERM_CFG1 0x00000673 178 #define MSR_CPU_THERM_CFG2 0x00000674 179 #define MSR_CPU_THERM_SENS_CFG 0x00000675 180 181 #define MSR_AMD64_MC0_MASK 0xc0010044 182 183 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 184 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 185 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 186 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 187 188 #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 189 190 /* These are consecutive and not in the normal 4er MCE bank block */ 191 #define MSR_IA32_MC0_CTL2 0x00000280 192 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 193 194 #define MSR_P6_PERFCTR0 0x000000c1 195 #define MSR_P6_PERFCTR1 0x000000c2 196 #define MSR_P6_EVNTSEL0 0x00000186 197 #define MSR_P6_EVNTSEL1 0x00000187 198 199 #define MSR_KNC_PERFCTR0 0x00000020 200 #define MSR_KNC_PERFCTR1 0x00000021 201 #define MSR_KNC_EVNTSEL0 0x00000028 202 #define MSR_KNC_EVNTSEL1 0x00000029 203 204 /* Alternative perfctr range with full access. */ 205 #define MSR_IA32_PMC0 0x000004c1 206 207 /* AMD64 MSRs. Not complete. See the architecture manual for a more 208 complete list. */ 209 210 #define MSR_AMD64_PATCH_LEVEL 0x0000008b 211 #define MSR_AMD64_TSC_RATIO 0xc0000104 212 #define MSR_AMD64_NB_CFG 0xc001001f 213 #define MSR_AMD64_PATCH_LOADER 0xc0010020 214 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 215 #define MSR_AMD64_OSVW_STATUS 0xc0010141 216 #define MSR_AMD64_LS_CFG 0xc0011020 217 #define MSR_AMD64_DC_CFG 0xc0011022 218 #define MSR_AMD64_BU_CFG2 0xc001102a 219 #define MSR_AMD64_IBSFETCHCTL 0xc0011030 220 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 221 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 222 #define MSR_AMD64_IBSFETCH_REG_COUNT 3 223 #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 224 #define MSR_AMD64_IBSOPCTL 0xc0011033 225 #define MSR_AMD64_IBSOPRIP 0xc0011034 226 #define MSR_AMD64_IBSOPDATA 0xc0011035 227 #define MSR_AMD64_IBSOPDATA2 0xc0011036 228 #define MSR_AMD64_IBSOPDATA3 0xc0011037 229 #define MSR_AMD64_IBSDCLINAD 0xc0011038 230 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 231 #define MSR_AMD64_IBSOP_REG_COUNT 7 232 #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 233 #define MSR_AMD64_IBSCTL 0xc001103a 234 #define MSR_AMD64_IBSBRTARGET 0xc001103b 235 #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 236 237 /* Fam 16h MSRs */ 238 #define MSR_F16H_L2I_PERF_CTL 0xc0010230 239 #define MSR_F16H_L2I_PERF_CTR 0xc0010231 240 241 /* Fam 15h MSRs */ 242 #define MSR_F15H_PERF_CTL 0xc0010200 243 #define MSR_F15H_PERF_CTR 0xc0010201 244 #define MSR_F15H_NB_PERF_CTL 0xc0010240 245 #define MSR_F15H_NB_PERF_CTR 0xc0010241 246 247 /* Fam 10h MSRs */ 248 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 249 #define FAM10H_MMIO_CONF_ENABLE (1<<0) 250 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 251 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 252 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 253 #define FAM10H_MMIO_CONF_BASE_SHIFT 20 254 #define MSR_FAM10H_NODE_ID 0xc001100c 255 256 /* K8 MSRs */ 257 #define MSR_K8_TOP_MEM1 0xc001001a 258 #define MSR_K8_TOP_MEM2 0xc001001d 259 #define MSR_K8_SYSCFG 0xc0010010 260 #define MSR_K8_INT_PENDING_MSG 0xc0010055 261 /* C1E active bits in int pending message */ 262 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 263 #define MSR_K8_TSEG_ADDR 0xc0010112 264 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 265 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 266 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 267 268 /* K7 MSRs */ 269 #define MSR_K7_EVNTSEL0 0xc0010000 270 #define MSR_K7_PERFCTR0 0xc0010004 271 #define MSR_K7_EVNTSEL1 0xc0010001 272 #define MSR_K7_PERFCTR1 0xc0010005 273 #define MSR_K7_EVNTSEL2 0xc0010002 274 #define MSR_K7_PERFCTR2 0xc0010006 275 #define MSR_K7_EVNTSEL3 0xc0010003 276 #define MSR_K7_PERFCTR3 0xc0010007 277 #define MSR_K7_CLK_CTL 0xc001001b 278 #define MSR_K7_HWCR 0xc0010015 279 #define MSR_K7_FID_VID_CTL 0xc0010041 280 #define MSR_K7_FID_VID_STATUS 0xc0010042 281 282 /* K6 MSRs */ 283 #define MSR_K6_WHCR 0xc0000082 284 #define MSR_K6_UWCCR 0xc0000085 285 #define MSR_K6_EPMR 0xc0000086 286 #define MSR_K6_PSOR 0xc0000087 287 #define MSR_K6_PFIR 0xc0000088 288 289 /* Centaur-Hauls/IDT defined MSRs. */ 290 #define MSR_IDT_FCR1 0x00000107 291 #define MSR_IDT_FCR2 0x00000108 292 #define MSR_IDT_FCR3 0x00000109 293 #define MSR_IDT_FCR4 0x0000010a 294 295 #define MSR_IDT_MCR0 0x00000110 296 #define MSR_IDT_MCR1 0x00000111 297 #define MSR_IDT_MCR2 0x00000112 298 #define MSR_IDT_MCR3 0x00000113 299 #define MSR_IDT_MCR4 0x00000114 300 #define MSR_IDT_MCR5 0x00000115 301 #define MSR_IDT_MCR6 0x00000116 302 #define MSR_IDT_MCR7 0x00000117 303 #define MSR_IDT_MCR_CTRL 0x00000120 304 305 /* VIA Cyrix defined MSRs*/ 306 #define MSR_VIA_FCR 0x00001107 307 #define MSR_VIA_LONGHAUL 0x0000110a 308 #define MSR_VIA_RNG 0x0000110b 309 #define MSR_VIA_BCR2 0x00001147 310 311 /* Transmeta defined MSRs */ 312 #define MSR_TMTA_LONGRUN_CTRL 0x80868010 313 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 314 #define MSR_TMTA_LRTI_READOUT 0x80868018 315 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 316 317 /* Intel defined MSRs. */ 318 #define MSR_IA32_P5_MC_ADDR 0x00000000 319 #define MSR_IA32_P5_MC_TYPE 0x00000001 320 #define MSR_IA32_TSC 0x00000010 321 #define MSR_IA32_PLATFORM_ID 0x00000017 322 #define MSR_IA32_EBL_CR_POWERON 0x0000002a 323 #define MSR_EBC_FREQUENCY_ID 0x0000002c 324 #define MSR_SMI_COUNT 0x00000034 325 #define MSR_IA32_FEATURE_CONTROL 0x0000003a 326 #define MSR_IA32_TSC_ADJUST 0x0000003b 327 328 #define FEATURE_CONTROL_LOCKED (1<<0) 329 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) 330 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 331 332 #define MSR_IA32_APICBASE 0x0000001b 333 #define MSR_IA32_APICBASE_BSP (1<<8) 334 #define MSR_IA32_APICBASE_ENABLE (1<<11) 335 #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 336 337 #define MSR_IA32_TSCDEADLINE 0x000006e0 338 339 #define MSR_IA32_UCODE_WRITE 0x00000079 340 #define MSR_IA32_UCODE_REV 0x0000008b 341 342 #define MSR_IA32_PERF_STATUS 0x00000198 343 #define MSR_IA32_PERF_CTL 0x00000199 344 #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 345 #define MSR_AMD_PERF_STATUS 0xc0010063 346 #define MSR_AMD_PERF_CTL 0xc0010062 347 348 #define MSR_PMG_CST_CONFIG_CTL 0x000000e2 349 #define MSR_PMG_IO_CAPTURE_ADR 0x000000e4 350 #define MSR_IA32_MPERF 0x000000e7 351 #define MSR_IA32_APERF 0x000000e8 352 353 #define MSR_IA32_THERM_CONTROL 0x0000019a 354 #define MSR_IA32_THERM_INTERRUPT 0x0000019b 355 356 #define THERM_INT_HIGH_ENABLE (1 << 0) 357 #define THERM_INT_LOW_ENABLE (1 << 1) 358 #define THERM_INT_PLN_ENABLE (1 << 24) 359 360 #define MSR_IA32_THERM_STATUS 0x0000019c 361 362 #define THERM_STATUS_PROCHOT (1 << 0) 363 #define THERM_STATUS_POWER_LIMIT (1 << 10) 364 365 #define MSR_THERM2_CTL 0x0000019d 366 367 #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 368 369 #define MSR_IA32_MISC_ENABLE 0x000001a0 370 #define H_MISC_DISABLE_TURBO (1 << 6) 371 372 #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 373 374 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 375 #define ENERGY_PERF_BIAS_PERFORMANCE 0 376 #define ENERGY_PERF_BIAS_NORMAL 6 377 #define ENERGY_PERF_BIAS_POWERSAVE 15 378 379 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 380 381 #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 382 #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 383 384 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 385 386 #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 387 #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 388 #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 389 390 /* Thermal Thresholds Support */ 391 #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 392 #define THERM_SHIFT_THRESHOLD0 8 393 #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 394 #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 395 #define THERM_SHIFT_THRESHOLD1 16 396 #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 397 #define THERM_STATUS_THRESHOLD0 (1 << 6) 398 #define THERM_LOG_THRESHOLD0 (1 << 7) 399 #define THERM_STATUS_THRESHOLD1 (1 << 8) 400 #define THERM_LOG_THRESHOLD1 (1 << 9) 401 402 /* MISC_ENABLE bits: architectural */ 403 #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0) 404 #define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1) 405 #define MSR_IA32_MISC_ENABLE_EMON (1ULL << 7) 406 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11) 407 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12) 408 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16) 409 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) 410 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << 22) 411 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << 23) 412 #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34) 413 414 /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 415 #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << 2) 416 #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << 3) 417 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4) 418 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << 6) 419 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << 8) 420 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << 9) 421 #define MSR_IA32_MISC_ENABLE_FERR (1ULL << 10) 422 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << 10) 423 #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << 13) 424 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << 19) 425 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << 20) 426 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << 24) 427 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << 37) 428 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38) 429 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39) 430 431 #define MSR_IA32_TSC_DEADLINE 0x000006E0 432 433 /* P4/Xeon+ specific */ 434 #define MSR_IA32_MCG_EAX 0x00000180 435 #define MSR_IA32_MCG_EBX 0x00000181 436 #define MSR_IA32_MCG_ECX 0x00000182 437 #define MSR_IA32_MCG_EDX 0x00000183 438 #define MSR_IA32_MCG_ESI 0x00000184 439 #define MSR_IA32_MCG_EDI 0x00000185 440 #define MSR_IA32_MCG_EBP 0x00000186 441 #define MSR_IA32_MCG_ESP 0x00000187 442 #define MSR_IA32_MCG_EFLAGS 0x00000188 443 #define MSR_IA32_MCG_EIP 0x00000189 444 #define MSR_IA32_MCG_RESERVED 0x0000018a 445 446 /* Pentium IV performance counter MSRs */ 447 #define MSR_P4_BPU_PERFCTR0 0x00000300 448 #define MSR_P4_BPU_PERFCTR1 0x00000301 449 #define MSR_P4_BPU_PERFCTR2 0x00000302 450 #define MSR_P4_BPU_PERFCTR3 0x00000303 451 #define MSR_P4_MS_PERFCTR0 0x00000304 452 #define MSR_P4_MS_PERFCTR1 0x00000305 453 #define MSR_P4_MS_PERFCTR2 0x00000306 454 #define MSR_P4_MS_PERFCTR3 0x00000307 455 #define MSR_P4_FLAME_PERFCTR0 0x00000308 456 #define MSR_P4_FLAME_PERFCTR1 0x00000309 457 #define MSR_P4_FLAME_PERFCTR2 0x0000030a 458 #define MSR_P4_FLAME_PERFCTR3 0x0000030b 459 #define MSR_P4_IQ_PERFCTR0 0x0000030c 460 #define MSR_P4_IQ_PERFCTR1 0x0000030d 461 #define MSR_P4_IQ_PERFCTR2 0x0000030e 462 #define MSR_P4_IQ_PERFCTR3 0x0000030f 463 #define MSR_P4_IQ_PERFCTR4 0x00000310 464 #define MSR_P4_IQ_PERFCTR5 0x00000311 465 #define MSR_P4_BPU_CCCR0 0x00000360 466 #define MSR_P4_BPU_CCCR1 0x00000361 467 #define MSR_P4_BPU_CCCR2 0x00000362 468 #define MSR_P4_BPU_CCCR3 0x00000363 469 #define MSR_P4_MS_CCCR0 0x00000364 470 #define MSR_P4_MS_CCCR1 0x00000365 471 #define MSR_P4_MS_CCCR2 0x00000366 472 #define MSR_P4_MS_CCCR3 0x00000367 473 #define MSR_P4_FLAME_CCCR0 0x00000368 474 #define MSR_P4_FLAME_CCCR1 0x00000369 475 #define MSR_P4_FLAME_CCCR2 0x0000036a 476 #define MSR_P4_FLAME_CCCR3 0x0000036b 477 #define MSR_P4_IQ_CCCR0 0x0000036c 478 #define MSR_P4_IQ_CCCR1 0x0000036d 479 #define MSR_P4_IQ_CCCR2 0x0000036e 480 #define MSR_P4_IQ_CCCR3 0x0000036f 481 #define MSR_P4_IQ_CCCR4 0x00000370 482 #define MSR_P4_IQ_CCCR5 0x00000371 483 #define MSR_P4_ALF_ESCR0 0x000003ca 484 #define MSR_P4_ALF_ESCR1 0x000003cb 485 #define MSR_P4_BPU_ESCR0 0x000003b2 486 #define MSR_P4_BPU_ESCR1 0x000003b3 487 #define MSR_P4_BSU_ESCR0 0x000003a0 488 #define MSR_P4_BSU_ESCR1 0x000003a1 489 #define MSR_P4_CRU_ESCR0 0x000003b8 490 #define MSR_P4_CRU_ESCR1 0x000003b9 491 #define MSR_P4_CRU_ESCR2 0x000003cc 492 #define MSR_P4_CRU_ESCR3 0x000003cd 493 #define MSR_P4_CRU_ESCR4 0x000003e0 494 #define MSR_P4_CRU_ESCR5 0x000003e1 495 #define MSR_P4_DAC_ESCR0 0x000003a8 496 #define MSR_P4_DAC_ESCR1 0x000003a9 497 #define MSR_P4_FIRM_ESCR0 0x000003a4 498 #define MSR_P4_FIRM_ESCR1 0x000003a5 499 #define MSR_P4_FLAME_ESCR0 0x000003a6 500 #define MSR_P4_FLAME_ESCR1 0x000003a7 501 #define MSR_P4_FSB_ESCR0 0x000003a2 502 #define MSR_P4_FSB_ESCR1 0x000003a3 503 #define MSR_P4_IQ_ESCR0 0x000003ba 504 #define MSR_P4_IQ_ESCR1 0x000003bb 505 #define MSR_P4_IS_ESCR0 0x000003b4 506 #define MSR_P4_IS_ESCR1 0x000003b5 507 #define MSR_P4_ITLB_ESCR0 0x000003b6 508 #define MSR_P4_ITLB_ESCR1 0x000003b7 509 #define MSR_P4_IX_ESCR0 0x000003c8 510 #define MSR_P4_IX_ESCR1 0x000003c9 511 #define MSR_P4_MOB_ESCR0 0x000003aa 512 #define MSR_P4_MOB_ESCR1 0x000003ab 513 #define MSR_P4_MS_ESCR0 0x000003c0 514 #define MSR_P4_MS_ESCR1 0x000003c1 515 #define MSR_P4_PMH_ESCR0 0x000003ac 516 #define MSR_P4_PMH_ESCR1 0x000003ad 517 #define MSR_P4_RAT_ESCR0 0x000003bc 518 #define MSR_P4_RAT_ESCR1 0x000003bd 519 #define MSR_P4_SAAT_ESCR0 0x000003ae 520 #define MSR_P4_SAAT_ESCR1 0x000003af 521 #define MSR_P4_SSU_ESCR0 0x000003be 522 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 523 524 #define MSR_P4_TBPU_ESCR0 0x000003c2 525 #define MSR_P4_TBPU_ESCR1 0x000003c3 526 #define MSR_P4_TC_ESCR0 0x000003c4 527 #define MSR_P4_TC_ESCR1 0x000003c5 528 #define MSR_P4_U2L_ESCR0 0x000003b0 529 #define MSR_P4_U2L_ESCR1 0x000003b1 530 531 #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 532 533 /* Intel Core-based CPU performance counters */ 534 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 535 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 536 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 537 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 538 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 539 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 540 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 541 542 /* Geode defined MSRs */ 543 #define MSR_GEODE_BUSCONT_CONF0 0x00001900 544 545 /* Intel VT MSRs */ 546 #define MSR_IA32_VMX_BASIC 0x00000480 547 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 548 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 549 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 550 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 551 #define MSR_IA32_VMX_MISC 0x00000485 552 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 553 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 554 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 555 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 556 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 557 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 558 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 559 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 560 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 561 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 562 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 563 #define MSR_IA32_VMX_VMFUNC 0x00000491 564 565 /* VMX_BASIC bits and bitmasks */ 566 #define VMX_BASIC_VMCS_SIZE_SHIFT 32 567 #define VMX_BASIC_64 0x0001000000000000LLU 568 #define VMX_BASIC_MEM_TYPE_SHIFT 50 569 #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 570 #define VMX_BASIC_MEM_TYPE_WB 6LLU 571 #define VMX_BASIC_INOUT 0x0040000000000000LLU 572 573 /* MSR_IA32_VMX_MISC bits */ 574 #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 575 #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 576 /* AMD-V MSRs */ 577 578 #define MSR_VM_CR 0xc0010114 579 #define MSR_VM_IGNNE 0xc0010115 580 #define MSR_VM_HSAVE_PA 0xc0010117 581 582 #endif /* _ASM_X86_MSR_INDEX_H */ 583