1 /* 2 * Taken from the linux kernel file of the same name 3 * 4 * (C) Copyright 2012 5 * Graeme Russ, <graeme.russ@gmail.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _ASM_X86_MSR_INDEX_H 11 #define _ASM_X86_MSR_INDEX_H 12 13 /* CPU model specific register (MSR) numbers */ 14 15 /* x86-64 specific MSRs */ 16 #define MSR_EFER 0xc0000080 /* extended feature register */ 17 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 18 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 19 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 20 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 21 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 22 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 23 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 24 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 25 26 /* EFER bits: */ 27 #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 28 #define _EFER_LME 8 /* Long mode enable */ 29 #define _EFER_LMA 10 /* Long mode active (read-only) */ 30 #define _EFER_NX 11 /* No execute enable */ 31 #define _EFER_SVME 12 /* Enable virtualization */ 32 #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 33 #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 34 35 #define EFER_SCE (1<<_EFER_SCE) 36 #define EFER_LME (1<<_EFER_LME) 37 #define EFER_LMA (1<<_EFER_LMA) 38 #define EFER_NX (1<<_EFER_NX) 39 #define EFER_SVME (1<<_EFER_SVME) 40 #define EFER_LMSLE (1<<_EFER_LMSLE) 41 #define EFER_FFXSR (1<<_EFER_FFXSR) 42 43 /* Intel MSRs. Some also available on other CPUs */ 44 #define MSR_PIC_MSG_CONTROL 0x2e 45 #define PLATFORM_INFO_SET_TDP (1 << 29) 46 47 #define MSR_IA32_PERFCTR0 0x000000c1 48 #define MSR_IA32_PERFCTR1 0x000000c2 49 #define MSR_FSB_FREQ 0x000000cd 50 #define MSR_NHM_PLATFORM_INFO 0x000000ce 51 52 #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 53 #define NHM_C3_AUTO_DEMOTE (1UL << 25) 54 #define NHM_C1_AUTO_DEMOTE (1UL << 26) 55 #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 56 #define SNB_C1_AUTO_UNDEMOTE (1UL << 27) 57 #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) 58 59 #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0x000000cd 60 #define MSR_PLATFORM_INFO 0x000000ce 61 #define MSR_PMG_CST_CONFIG_CONTROL 0x000000e2 62 #define SINGLE_PCTL (1 << 11) 63 64 #define MSR_MTRRcap 0x000000fe 65 #define MSR_IA32_BBL_CR_CTL 0x00000119 66 #define MSR_IA32_BBL_CR_CTL3 0x0000011e 67 #define MSR_POWER_MISC 0x00000120 68 #define ENABLE_ULFM_AUTOCM_MASK (1 << 2) 69 #define ENABLE_INDP_AUTOCM_MASK (1 << 3) 70 71 #define MSR_IA32_SYSENTER_CS 0x00000174 72 #define MSR_IA32_SYSENTER_ESP 0x00000175 73 #define MSR_IA32_SYSENTER_EIP 0x00000176 74 75 #define MSR_IA32_MCG_CAP 0x00000179 76 #define MSR_IA32_MCG_STATUS 0x0000017a 77 #define MSR_IA32_MCG_CTL 0x0000017b 78 79 #define MSR_FLEX_RATIO 0x194 80 #define FLEX_RATIO_LOCK (1 << 20) 81 #define FLEX_RATIO_EN (1 << 16) 82 83 #define MSR_IA32_MISC_ENABLES 0x000001a0 84 #define MSR_TEMPERATURE_TARGET 0x1a2 85 #define MSR_OFFCORE_RSP_0 0x000001a6 86 #define MSR_OFFCORE_RSP_1 0x000001a7 87 #define MSR_MISC_PWR_MGMT 0x1aa 88 #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) 89 #define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad 90 #define MSR_IVT_TURBO_RATIO_LIMIT 0x000001ae 91 92 #define MSR_IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 93 #define ENERGY_POLICY_PERFORMANCE 0 94 #define ENERGY_POLICY_NORMAL 6 95 #define ENERGY_POLICY_POWERSAVE 15 96 97 #define MSR_LBR_SELECT 0x000001c8 98 #define MSR_LBR_TOS 0x000001c9 99 #define MSR_IA32_PLATFORM_DCA_CAP 0x1f8 100 #define MSR_POWER_CTL 0x000001fc 101 #define MSR_LBR_NHM_FROM 0x00000680 102 #define MSR_LBR_NHM_TO 0x000006c0 103 #define MSR_LBR_CORE_FROM 0x00000040 104 #define MSR_LBR_CORE_TO 0x00000060 105 106 #define MSR_IA32_PEBS_ENABLE 0x000003f1 107 #define MSR_IA32_DS_AREA 0x00000600 108 #define MSR_IA32_PERF_CAPABILITIES 0x00000345 109 #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 110 111 #define MSR_MTRRfix64K_00000 0x00000250 112 #define MSR_MTRRfix16K_80000 0x00000258 113 #define MSR_MTRRfix16K_A0000 0x00000259 114 #define MSR_MTRRfix4K_C0000 0x00000268 115 #define MSR_MTRRfix4K_C8000 0x00000269 116 #define MSR_MTRRfix4K_D0000 0x0000026a 117 #define MSR_MTRRfix4K_D8000 0x0000026b 118 #define MSR_MTRRfix4K_E0000 0x0000026c 119 #define MSR_MTRRfix4K_E8000 0x0000026d 120 #define MSR_MTRRfix4K_F0000 0x0000026e 121 #define MSR_MTRRfix4K_F8000 0x0000026f 122 #define MSR_MTRRdefType 0x000002ff 123 124 #define MSR_IA32_CR_PAT 0x00000277 125 126 #define MSR_IA32_DEBUGCTLMSR 0x000001d9 127 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 128 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 129 #define MSR_IA32_LASTINTFROMIP 0x000001dd 130 #define MSR_IA32_LASTINTTOIP 0x000001de 131 132 /* DEBUGCTLMSR bits (others vary by model): */ 133 #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 134 /* single-step on branches */ 135 #define DEBUGCTLMSR_BTF (1UL << 1) 136 #define DEBUGCTLMSR_TR (1UL << 6) 137 #define DEBUGCTLMSR_BTS (1UL << 7) 138 #define DEBUGCTLMSR_BTINT (1UL << 8) 139 #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 140 #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 141 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 142 143 #define MSR_IA32_POWER_CTL 0x000001fc 144 145 #define MSR_IA32_MC0_CTL 0x00000400 146 #define MSR_IA32_MC0_STATUS 0x00000401 147 #define MSR_IA32_MC0_ADDR 0x00000402 148 #define MSR_IA32_MC0_MISC 0x00000403 149 150 /* C-state Residency Counters */ 151 #define MSR_PKG_C3_RESIDENCY 0x000003f8 152 #define MSR_PKG_C6_RESIDENCY 0x000003f9 153 #define MSR_PKG_C7_RESIDENCY 0x000003fa 154 #define MSR_CORE_C3_RESIDENCY 0x000003fc 155 #define MSR_CORE_C6_RESIDENCY 0x000003fd 156 #define MSR_CORE_C7_RESIDENCY 0x000003fe 157 #define MSR_PKG_C2_RESIDENCY 0x0000060d 158 #define MSR_PKG_C8_RESIDENCY 0x00000630 159 #define MSR_PKG_C9_RESIDENCY 0x00000631 160 #define MSR_PKG_C10_RESIDENCY 0x00000632 161 162 /* Run Time Average Power Limiting (RAPL) Interface */ 163 164 #define MSR_PKG_POWER_SKU_UNIT 0x00000606 165 166 #define MSR_C_STATE_LATENCY_CONTROL_0 0x60a 167 #define MSR_C_STATE_LATENCY_CONTROL_1 0x60b 168 #define MSR_C_STATE_LATENCY_CONTROL_2 0x60c 169 #define MSR_C_STATE_LATENCY_CONTROL_3 0x633 170 #define MSR_C_STATE_LATENCY_CONTROL_4 0x634 171 #define MSR_C_STATE_LATENCY_CONTROL_5 0x635 172 #define IRTL_VALID (1 << 15) 173 #define IRTL_1_NS (0 << 10) 174 #define IRTL_32_NS (1 << 10) 175 #define IRTL_1024_NS (2 << 10) 176 #define IRTL_32768_NS (3 << 10) 177 #define IRTL_1048576_NS (4 << 10) 178 #define IRTL_33554432_NS (5 << 10) 179 #define IRTL_RESPONSE_MASK (0x3ff) 180 181 #define MSR_PKG_POWER_LIMIT 0x00000610 182 /* long duration in low dword, short duration in high dword */ 183 #define PKG_POWER_LIMIT_MASK 0x7fff 184 #define PKG_POWER_LIMIT_EN (1 << 15) 185 #define PKG_POWER_LIMIT_CLAMP (1 << 16) 186 #define PKG_POWER_LIMIT_TIME_SHIFT 17 187 #define PKG_POWER_LIMIT_TIME_MASK 0x7f 188 189 #define MSR_PKG_ENERGY_STATUS 0x00000611 190 #define MSR_PKG_PERF_STATUS 0x00000613 191 #define MSR_PKG_POWER_INFO 0x00000614 192 193 #define MSR_DRAM_POWER_LIMIT 0x00000618 194 #define MSR_DRAM_ENERGY_STATUS 0x00000619 195 #define MSR_DRAM_PERF_STATUS 0x0000061b 196 #define MSR_DRAM_POWER_INFO 0x0000061c 197 198 #define MSR_PP0_POWER_LIMIT 0x00000638 199 #define MSR_PP0_ENERGY_STATUS 0x00000639 200 #define MSR_PP0_POLICY 0x0000063a 201 #define MSR_PP0_PERF_STATUS 0x0000063b 202 203 #define MSR_PP1_POWER_LIMIT 0x00000640 204 #define MSR_PP1_ENERGY_STATUS 0x00000641 205 #define MSR_PP1_POLICY 0x00000642 206 #define MSR_CONFIG_TDP_NOMINAL 0x00000648 207 #define MSR_TURBO_ACTIVATION_RATIO 0x0000064c 208 #define MSR_CORE_C1_RES 0x00000660 209 #define MSR_IACORE_RATIOS 0x0000066a 210 #define MSR_IACORE_TURBO_RATIOS 0x0000066c 211 #define MSR_IACORE_VIDS 0x0000066b 212 #define MSR_IACORE_TURBO_VIDS 0x0000066d 213 #define MSR_PKG_TURBO_CFG1 0x00000670 214 #define MSR_CPU_TURBO_WKLD_CFG1 0x00000671 215 #define MSR_CPU_TURBO_WKLD_CFG2 0x00000672 216 #define MSR_CPU_THERM_CFG1 0x00000673 217 #define MSR_CPU_THERM_CFG2 0x00000674 218 #define MSR_CPU_THERM_SENS_CFG 0x00000675 219 220 #define MSR_AMD64_MC0_MASK 0xc0010044 221 222 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 223 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 224 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 225 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 226 227 #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 228 229 /* These are consecutive and not in the normal 4er MCE bank block */ 230 #define MSR_IA32_MC0_CTL2 0x00000280 231 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 232 233 #define MSR_P6_PERFCTR0 0x000000c1 234 #define MSR_P6_PERFCTR1 0x000000c2 235 #define MSR_P6_EVNTSEL0 0x00000186 236 #define MSR_P6_EVNTSEL1 0x00000187 237 238 #define MSR_KNC_PERFCTR0 0x00000020 239 #define MSR_KNC_PERFCTR1 0x00000021 240 #define MSR_KNC_EVNTSEL0 0x00000028 241 #define MSR_KNC_EVNTSEL1 0x00000029 242 243 /* Alternative perfctr range with full access. */ 244 #define MSR_IA32_PMC0 0x000004c1 245 246 /* AMD64 MSRs. Not complete. See the architecture manual for a more 247 complete list. */ 248 249 #define MSR_AMD64_PATCH_LEVEL 0x0000008b 250 #define MSR_AMD64_TSC_RATIO 0xc0000104 251 #define MSR_AMD64_NB_CFG 0xc001001f 252 #define MSR_AMD64_PATCH_LOADER 0xc0010020 253 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 254 #define MSR_AMD64_OSVW_STATUS 0xc0010141 255 #define MSR_AMD64_LS_CFG 0xc0011020 256 #define MSR_AMD64_DC_CFG 0xc0011022 257 #define MSR_AMD64_BU_CFG2 0xc001102a 258 #define MSR_AMD64_IBSFETCHCTL 0xc0011030 259 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 260 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 261 #define MSR_AMD64_IBSFETCH_REG_COUNT 3 262 #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 263 #define MSR_AMD64_IBSOPCTL 0xc0011033 264 #define MSR_AMD64_IBSOPRIP 0xc0011034 265 #define MSR_AMD64_IBSOPDATA 0xc0011035 266 #define MSR_AMD64_IBSOPDATA2 0xc0011036 267 #define MSR_AMD64_IBSOPDATA3 0xc0011037 268 #define MSR_AMD64_IBSDCLINAD 0xc0011038 269 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 270 #define MSR_AMD64_IBSOP_REG_COUNT 7 271 #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 272 #define MSR_AMD64_IBSCTL 0xc001103a 273 #define MSR_AMD64_IBSBRTARGET 0xc001103b 274 #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 275 276 /* Fam 16h MSRs */ 277 #define MSR_F16H_L2I_PERF_CTL 0xc0010230 278 #define MSR_F16H_L2I_PERF_CTR 0xc0010231 279 280 /* Fam 15h MSRs */ 281 #define MSR_F15H_PERF_CTL 0xc0010200 282 #define MSR_F15H_PERF_CTR 0xc0010201 283 #define MSR_F15H_NB_PERF_CTL 0xc0010240 284 #define MSR_F15H_NB_PERF_CTR 0xc0010241 285 286 /* Fam 10h MSRs */ 287 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 288 #define FAM10H_MMIO_CONF_ENABLE (1<<0) 289 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 290 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 291 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 292 #define FAM10H_MMIO_CONF_BASE_SHIFT 20 293 #define MSR_FAM10H_NODE_ID 0xc001100c 294 295 /* K8 MSRs */ 296 #define MSR_K8_TOP_MEM1 0xc001001a 297 #define MSR_K8_TOP_MEM2 0xc001001d 298 #define MSR_K8_SYSCFG 0xc0010010 299 #define MSR_K8_INT_PENDING_MSG 0xc0010055 300 /* C1E active bits in int pending message */ 301 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 302 #define MSR_K8_TSEG_ADDR 0xc0010112 303 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 304 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 305 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 306 307 /* K7 MSRs */ 308 #define MSR_K7_EVNTSEL0 0xc0010000 309 #define MSR_K7_PERFCTR0 0xc0010004 310 #define MSR_K7_EVNTSEL1 0xc0010001 311 #define MSR_K7_PERFCTR1 0xc0010005 312 #define MSR_K7_EVNTSEL2 0xc0010002 313 #define MSR_K7_PERFCTR2 0xc0010006 314 #define MSR_K7_EVNTSEL3 0xc0010003 315 #define MSR_K7_PERFCTR3 0xc0010007 316 #define MSR_K7_CLK_CTL 0xc001001b 317 #define MSR_K7_HWCR 0xc0010015 318 #define MSR_K7_FID_VID_CTL 0xc0010041 319 #define MSR_K7_FID_VID_STATUS 0xc0010042 320 321 /* K6 MSRs */ 322 #define MSR_K6_WHCR 0xc0000082 323 #define MSR_K6_UWCCR 0xc0000085 324 #define MSR_K6_EPMR 0xc0000086 325 #define MSR_K6_PSOR 0xc0000087 326 #define MSR_K6_PFIR 0xc0000088 327 328 /* Centaur-Hauls/IDT defined MSRs. */ 329 #define MSR_IDT_FCR1 0x00000107 330 #define MSR_IDT_FCR2 0x00000108 331 #define MSR_IDT_FCR3 0x00000109 332 #define MSR_IDT_FCR4 0x0000010a 333 334 #define MSR_IDT_MCR0 0x00000110 335 #define MSR_IDT_MCR1 0x00000111 336 #define MSR_IDT_MCR2 0x00000112 337 #define MSR_IDT_MCR3 0x00000113 338 #define MSR_IDT_MCR4 0x00000114 339 #define MSR_IDT_MCR5 0x00000115 340 #define MSR_IDT_MCR6 0x00000116 341 #define MSR_IDT_MCR7 0x00000117 342 #define MSR_IDT_MCR_CTRL 0x00000120 343 344 /* VIA Cyrix defined MSRs*/ 345 #define MSR_VIA_FCR 0x00001107 346 #define MSR_VIA_LONGHAUL 0x0000110a 347 #define MSR_VIA_RNG 0x0000110b 348 #define MSR_VIA_BCR2 0x00001147 349 350 /* Transmeta defined MSRs */ 351 #define MSR_TMTA_LONGRUN_CTRL 0x80868010 352 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 353 #define MSR_TMTA_LRTI_READOUT 0x80868018 354 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 355 356 /* Intel defined MSRs. */ 357 #define MSR_IA32_P5_MC_ADDR 0x00000000 358 #define MSR_IA32_P5_MC_TYPE 0x00000001 359 #define MSR_IA32_TSC 0x00000010 360 #define MSR_IA32_PLATFORM_ID 0x00000017 361 #define MSR_IA32_EBL_CR_POWERON 0x0000002a 362 #define MSR_EBC_FREQUENCY_ID 0x0000002c 363 #define MSR_SMI_COUNT 0x00000034 364 #define MSR_IA32_FEATURE_CONTROL 0x0000003a 365 #define MSR_IA32_TSC_ADJUST 0x0000003b 366 367 #define FEATURE_CONTROL_LOCKED (1<<0) 368 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) 369 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 370 371 #define MSR_IA32_APICBASE 0x0000001b 372 #define MSR_IA32_APICBASE_BSP (1<<8) 373 #define MSR_IA32_APICBASE_ENABLE (1<<11) 374 #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 375 376 #define MSR_IA32_TSCDEADLINE 0x000006e0 377 378 #define MSR_IA32_UCODE_WRITE 0x00000079 379 #define MSR_IA32_UCODE_REV 0x0000008b 380 381 #define MSR_IA32_PERF_STATUS 0x00000198 382 #define MSR_IA32_PERF_CTL 0x00000199 383 #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 384 #define MSR_AMD_PERF_STATUS 0xc0010063 385 #define MSR_AMD_PERF_CTL 0xc0010062 386 387 #define MSR_PMG_CST_CONFIG_CTL 0x000000e2 388 #define MSR_PMG_IO_CAPTURE_ADR 0x000000e4 389 #define MSR_IA32_MPERF 0x000000e7 390 #define MSR_IA32_APERF 0x000000e8 391 392 #define MSR_IA32_THERM_CONTROL 0x0000019a 393 #define MSR_IA32_THERM_INTERRUPT 0x0000019b 394 395 #define THERM_INT_HIGH_ENABLE (1 << 0) 396 #define THERM_INT_LOW_ENABLE (1 << 1) 397 #define THERM_INT_PLN_ENABLE (1 << 24) 398 399 #define MSR_IA32_THERM_STATUS 0x0000019c 400 401 #define THERM_STATUS_PROCHOT (1 << 0) 402 #define THERM_STATUS_POWER_LIMIT (1 << 10) 403 404 #define MSR_THERM2_CTL 0x0000019d 405 406 #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 407 408 #define MSR_IA32_MISC_ENABLE 0x000001a0 409 #define H_MISC_DISABLE_TURBO (1 << 6) 410 411 #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 412 413 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 414 #define ENERGY_PERF_BIAS_PERFORMANCE 0 415 #define ENERGY_PERF_BIAS_NORMAL 6 416 #define ENERGY_PERF_BIAS_POWERSAVE 15 417 418 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 419 420 #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 421 #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 422 423 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 424 425 #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 426 #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 427 #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 428 429 /* Thermal Thresholds Support */ 430 #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 431 #define THERM_SHIFT_THRESHOLD0 8 432 #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 433 #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 434 #define THERM_SHIFT_THRESHOLD1 16 435 #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 436 #define THERM_STATUS_THRESHOLD0 (1 << 6) 437 #define THERM_LOG_THRESHOLD0 (1 << 7) 438 #define THERM_STATUS_THRESHOLD1 (1 << 8) 439 #define THERM_LOG_THRESHOLD1 (1 << 9) 440 441 /* MISC_ENABLE bits: architectural */ 442 #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0) 443 #define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1) 444 #define MSR_IA32_MISC_ENABLE_EMON (1ULL << 7) 445 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11) 446 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12) 447 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16) 448 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) 449 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << 22) 450 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << 23) 451 #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34) 452 453 /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 454 #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << 2) 455 #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << 3) 456 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4) 457 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << 6) 458 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << 8) 459 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << 9) 460 #define MSR_IA32_MISC_ENABLE_FERR (1ULL << 10) 461 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << 10) 462 #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << 13) 463 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << 19) 464 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << 20) 465 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << 24) 466 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << 37) 467 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38) 468 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39) 469 470 #define MSR_IA32_TSC_DEADLINE 0x000006E0 471 472 /* P4/Xeon+ specific */ 473 #define MSR_IA32_MCG_EAX 0x00000180 474 #define MSR_IA32_MCG_EBX 0x00000181 475 #define MSR_IA32_MCG_ECX 0x00000182 476 #define MSR_IA32_MCG_EDX 0x00000183 477 #define MSR_IA32_MCG_ESI 0x00000184 478 #define MSR_IA32_MCG_EDI 0x00000185 479 #define MSR_IA32_MCG_EBP 0x00000186 480 #define MSR_IA32_MCG_ESP 0x00000187 481 #define MSR_IA32_MCG_EFLAGS 0x00000188 482 #define MSR_IA32_MCG_EIP 0x00000189 483 #define MSR_IA32_MCG_RESERVED 0x0000018a 484 485 /* Pentium IV performance counter MSRs */ 486 #define MSR_P4_BPU_PERFCTR0 0x00000300 487 #define MSR_P4_BPU_PERFCTR1 0x00000301 488 #define MSR_P4_BPU_PERFCTR2 0x00000302 489 #define MSR_P4_BPU_PERFCTR3 0x00000303 490 #define MSR_P4_MS_PERFCTR0 0x00000304 491 #define MSR_P4_MS_PERFCTR1 0x00000305 492 #define MSR_P4_MS_PERFCTR2 0x00000306 493 #define MSR_P4_MS_PERFCTR3 0x00000307 494 #define MSR_P4_FLAME_PERFCTR0 0x00000308 495 #define MSR_P4_FLAME_PERFCTR1 0x00000309 496 #define MSR_P4_FLAME_PERFCTR2 0x0000030a 497 #define MSR_P4_FLAME_PERFCTR3 0x0000030b 498 #define MSR_P4_IQ_PERFCTR0 0x0000030c 499 #define MSR_P4_IQ_PERFCTR1 0x0000030d 500 #define MSR_P4_IQ_PERFCTR2 0x0000030e 501 #define MSR_P4_IQ_PERFCTR3 0x0000030f 502 #define MSR_P4_IQ_PERFCTR4 0x00000310 503 #define MSR_P4_IQ_PERFCTR5 0x00000311 504 #define MSR_P4_BPU_CCCR0 0x00000360 505 #define MSR_P4_BPU_CCCR1 0x00000361 506 #define MSR_P4_BPU_CCCR2 0x00000362 507 #define MSR_P4_BPU_CCCR3 0x00000363 508 #define MSR_P4_MS_CCCR0 0x00000364 509 #define MSR_P4_MS_CCCR1 0x00000365 510 #define MSR_P4_MS_CCCR2 0x00000366 511 #define MSR_P4_MS_CCCR3 0x00000367 512 #define MSR_P4_FLAME_CCCR0 0x00000368 513 #define MSR_P4_FLAME_CCCR1 0x00000369 514 #define MSR_P4_FLAME_CCCR2 0x0000036a 515 #define MSR_P4_FLAME_CCCR3 0x0000036b 516 #define MSR_P4_IQ_CCCR0 0x0000036c 517 #define MSR_P4_IQ_CCCR1 0x0000036d 518 #define MSR_P4_IQ_CCCR2 0x0000036e 519 #define MSR_P4_IQ_CCCR3 0x0000036f 520 #define MSR_P4_IQ_CCCR4 0x00000370 521 #define MSR_P4_IQ_CCCR5 0x00000371 522 #define MSR_P4_ALF_ESCR0 0x000003ca 523 #define MSR_P4_ALF_ESCR1 0x000003cb 524 #define MSR_P4_BPU_ESCR0 0x000003b2 525 #define MSR_P4_BPU_ESCR1 0x000003b3 526 #define MSR_P4_BSU_ESCR0 0x000003a0 527 #define MSR_P4_BSU_ESCR1 0x000003a1 528 #define MSR_P4_CRU_ESCR0 0x000003b8 529 #define MSR_P4_CRU_ESCR1 0x000003b9 530 #define MSR_P4_CRU_ESCR2 0x000003cc 531 #define MSR_P4_CRU_ESCR3 0x000003cd 532 #define MSR_P4_CRU_ESCR4 0x000003e0 533 #define MSR_P4_CRU_ESCR5 0x000003e1 534 #define MSR_P4_DAC_ESCR0 0x000003a8 535 #define MSR_P4_DAC_ESCR1 0x000003a9 536 #define MSR_P4_FIRM_ESCR0 0x000003a4 537 #define MSR_P4_FIRM_ESCR1 0x000003a5 538 #define MSR_P4_FLAME_ESCR0 0x000003a6 539 #define MSR_P4_FLAME_ESCR1 0x000003a7 540 #define MSR_P4_FSB_ESCR0 0x000003a2 541 #define MSR_P4_FSB_ESCR1 0x000003a3 542 #define MSR_P4_IQ_ESCR0 0x000003ba 543 #define MSR_P4_IQ_ESCR1 0x000003bb 544 #define MSR_P4_IS_ESCR0 0x000003b4 545 #define MSR_P4_IS_ESCR1 0x000003b5 546 #define MSR_P4_ITLB_ESCR0 0x000003b6 547 #define MSR_P4_ITLB_ESCR1 0x000003b7 548 #define MSR_P4_IX_ESCR0 0x000003c8 549 #define MSR_P4_IX_ESCR1 0x000003c9 550 #define MSR_P4_MOB_ESCR0 0x000003aa 551 #define MSR_P4_MOB_ESCR1 0x000003ab 552 #define MSR_P4_MS_ESCR0 0x000003c0 553 #define MSR_P4_MS_ESCR1 0x000003c1 554 #define MSR_P4_PMH_ESCR0 0x000003ac 555 #define MSR_P4_PMH_ESCR1 0x000003ad 556 #define MSR_P4_RAT_ESCR0 0x000003bc 557 #define MSR_P4_RAT_ESCR1 0x000003bd 558 #define MSR_P4_SAAT_ESCR0 0x000003ae 559 #define MSR_P4_SAAT_ESCR1 0x000003af 560 #define MSR_P4_SSU_ESCR0 0x000003be 561 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 562 563 #define MSR_P4_TBPU_ESCR0 0x000003c2 564 #define MSR_P4_TBPU_ESCR1 0x000003c3 565 #define MSR_P4_TC_ESCR0 0x000003c4 566 #define MSR_P4_TC_ESCR1 0x000003c5 567 #define MSR_P4_U2L_ESCR0 0x000003b0 568 #define MSR_P4_U2L_ESCR1 0x000003b1 569 570 #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 571 572 /* Intel Core-based CPU performance counters */ 573 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 574 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 575 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 576 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 577 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 578 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 579 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 580 581 /* Geode defined MSRs */ 582 #define MSR_GEODE_BUSCONT_CONF0 0x00001900 583 584 /* Intel VT MSRs */ 585 #define MSR_IA32_VMX_BASIC 0x00000480 586 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 587 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 588 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 589 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 590 #define MSR_IA32_VMX_MISC 0x00000485 591 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 592 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 593 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 594 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 595 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 596 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 597 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 598 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 599 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 600 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 601 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 602 #define MSR_IA32_VMX_VMFUNC 0x00000491 603 604 /* VMX_BASIC bits and bitmasks */ 605 #define VMX_BASIC_VMCS_SIZE_SHIFT 32 606 #define VMX_BASIC_64 0x0001000000000000LLU 607 #define VMX_BASIC_MEM_TYPE_SHIFT 50 608 #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 609 #define VMX_BASIC_MEM_TYPE_WB 6LLU 610 #define VMX_BASIC_INOUT 0x0040000000000000LLU 611 612 /* MSR_IA32_VMX_MISC bits */ 613 #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 614 #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 615 /* AMD-V MSRs */ 616 617 #define MSR_VM_CR 0xc0010114 618 #define MSR_VM_IGNNE 0xc0010115 619 #define MSR_VM_HSAVE_PA 0xc0010117 620 621 #endif /* _ASM_X86_MSR_INDEX_H */ 622