1 /* 2 * Taken from the linux kernel file of the same name 3 * 4 * (C) Copyright 2012 5 * Graeme Russ, <graeme.russ@gmail.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef _ASM_X86_MSR_INDEX_H 24 #define _ASM_X86_MSR_INDEX_H 25 26 /* CPU model specific register (MSR) numbers */ 27 28 /* x86-64 specific MSRs */ 29 #define MSR_EFER 0xc0000080 /* extended feature register */ 30 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 31 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 32 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 33 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 34 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 35 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 36 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 37 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 38 39 /* EFER bits: */ 40 #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 41 #define _EFER_LME 8 /* Long mode enable */ 42 #define _EFER_LMA 10 /* Long mode active (read-only) */ 43 #define _EFER_NX 11 /* No execute enable */ 44 #define _EFER_SVME 12 /* Enable virtualization */ 45 #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 46 #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 47 48 #define EFER_SCE (1<<_EFER_SCE) 49 #define EFER_LME (1<<_EFER_LME) 50 #define EFER_LMA (1<<_EFER_LMA) 51 #define EFER_NX (1<<_EFER_NX) 52 #define EFER_SVME (1<<_EFER_SVME) 53 #define EFER_LMSLE (1<<_EFER_LMSLE) 54 #define EFER_FFXSR (1<<_EFER_FFXSR) 55 56 /* Intel MSRs. Some also available on other CPUs */ 57 #define MSR_IA32_PERFCTR0 0x000000c1 58 #define MSR_IA32_PERFCTR1 0x000000c2 59 #define MSR_FSB_FREQ 0x000000cd 60 61 #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 62 #define NHM_C3_AUTO_DEMOTE (1UL << 25) 63 #define NHM_C1_AUTO_DEMOTE (1UL << 26) 64 #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 65 66 #define MSR_MTRRcap 0x000000fe 67 #define MSR_IA32_BBL_CR_CTL 0x00000119 68 #define MSR_IA32_BBL_CR_CTL3 0x0000011e 69 70 #define MSR_IA32_SYSENTER_CS 0x00000174 71 #define MSR_IA32_SYSENTER_ESP 0x00000175 72 #define MSR_IA32_SYSENTER_EIP 0x00000176 73 74 #define MSR_IA32_MCG_CAP 0x00000179 75 #define MSR_IA32_MCG_STATUS 0x0000017a 76 #define MSR_IA32_MCG_CTL 0x0000017b 77 78 #define MSR_OFFCORE_RSP_0 0x000001a6 79 #define MSR_OFFCORE_RSP_1 0x000001a7 80 81 #define MSR_IA32_PEBS_ENABLE 0x000003f1 82 #define MSR_IA32_DS_AREA 0x00000600 83 #define MSR_IA32_PERF_CAPABILITIES 0x00000345 84 85 #define MSR_MTRRfix64K_00000 0x00000250 86 #define MSR_MTRRfix16K_80000 0x00000258 87 #define MSR_MTRRfix16K_A0000 0x00000259 88 #define MSR_MTRRfix4K_C0000 0x00000268 89 #define MSR_MTRRfix4K_C8000 0x00000269 90 #define MSR_MTRRfix4K_D0000 0x0000026a 91 #define MSR_MTRRfix4K_D8000 0x0000026b 92 #define MSR_MTRRfix4K_E0000 0x0000026c 93 #define MSR_MTRRfix4K_E8000 0x0000026d 94 #define MSR_MTRRfix4K_F0000 0x0000026e 95 #define MSR_MTRRfix4K_F8000 0x0000026f 96 #define MSR_MTRRdefType 0x000002ff 97 98 #define MSR_IA32_CR_PAT 0x00000277 99 100 #define MSR_IA32_DEBUGCTLMSR 0x000001d9 101 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 102 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 103 #define MSR_IA32_LASTINTFROMIP 0x000001dd 104 #define MSR_IA32_LASTINTTOIP 0x000001de 105 106 /* DEBUGCTLMSR bits (others vary by model): */ 107 #define DEBUGCTLMSR_LBR (1UL << 0) 108 #define DEBUGCTLMSR_BTF (1UL << 1) 109 #define DEBUGCTLMSR_TR (1UL << 6) 110 #define DEBUGCTLMSR_BTS (1UL << 7) 111 #define DEBUGCTLMSR_BTINT (1UL << 8) 112 #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 113 #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 114 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 115 116 #define MSR_IA32_MC0_CTL 0x00000400 117 #define MSR_IA32_MC0_STATUS 0x00000401 118 #define MSR_IA32_MC0_ADDR 0x00000402 119 #define MSR_IA32_MC0_MISC 0x00000403 120 121 #define MSR_AMD64_MC0_MASK 0xc0010044 122 123 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 124 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 125 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 126 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 127 128 #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 129 130 /* These are consecutive and not in the normal 4er MCE bank block */ 131 #define MSR_IA32_MC0_CTL2 0x00000280 132 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 133 134 #define MSR_P6_PERFCTR0 0x000000c1 135 #define MSR_P6_PERFCTR1 0x000000c2 136 #define MSR_P6_EVNTSEL0 0x00000186 137 #define MSR_P6_EVNTSEL1 0x00000187 138 139 /* AMD64 MSRs. Not complete. See the architecture manual for a more 140 complete list. */ 141 142 #define MSR_AMD64_PATCH_LEVEL 0x0000008b 143 #define MSR_AMD64_NB_CFG 0xc001001f 144 #define MSR_AMD64_PATCH_LOADER 0xc0010020 145 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 146 #define MSR_AMD64_OSVW_STATUS 0xc0010141 147 #define MSR_AMD64_DC_CFG 0xc0011022 148 #define MSR_AMD64_IBSFETCHCTL 0xc0011030 149 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 150 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 151 #define MSR_AMD64_IBSOPCTL 0xc0011033 152 #define MSR_AMD64_IBSOPRIP 0xc0011034 153 #define MSR_AMD64_IBSOPDATA 0xc0011035 154 #define MSR_AMD64_IBSOPDATA2 0xc0011036 155 #define MSR_AMD64_IBSOPDATA3 0xc0011037 156 #define MSR_AMD64_IBSDCLINAD 0xc0011038 157 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 158 #define MSR_AMD64_IBSCTL 0xc001103a 159 #define MSR_AMD64_IBSBRTARGET 0xc001103b 160 161 /* Fam 15h MSRs */ 162 #define MSR_F15H_PERF_CTL 0xc0010200 163 #define MSR_F15H_PERF_CTR 0xc0010201 164 165 /* Fam 10h MSRs */ 166 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 167 #define FAM10H_MMIO_CONF_ENABLE (1<<0) 168 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 169 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 170 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 171 #define FAM10H_MMIO_CONF_BASE_SHIFT 20 172 #define MSR_FAM10H_NODE_ID 0xc001100c 173 174 /* K8 MSRs */ 175 #define MSR_K8_TOP_MEM1 0xc001001a 176 #define MSR_K8_TOP_MEM2 0xc001001d 177 #define MSR_K8_SYSCFG 0xc0010010 178 #define MSR_K8_INT_PENDING_MSG 0xc0010055 179 /* C1E active bits in int pending message */ 180 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 181 #define MSR_K8_TSEG_ADDR 0xc0010112 182 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 183 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 184 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 185 186 /* K7 MSRs */ 187 #define MSR_K7_EVNTSEL0 0xc0010000 188 #define MSR_K7_PERFCTR0 0xc0010004 189 #define MSR_K7_EVNTSEL1 0xc0010001 190 #define MSR_K7_PERFCTR1 0xc0010005 191 #define MSR_K7_EVNTSEL2 0xc0010002 192 #define MSR_K7_PERFCTR2 0xc0010006 193 #define MSR_K7_EVNTSEL3 0xc0010003 194 #define MSR_K7_PERFCTR3 0xc0010007 195 #define MSR_K7_CLK_CTL 0xc001001b 196 #define MSR_K7_HWCR 0xc0010015 197 #define MSR_K7_FID_VID_CTL 0xc0010041 198 #define MSR_K7_FID_VID_STATUS 0xc0010042 199 200 /* K6 MSRs */ 201 #define MSR_K6_WHCR 0xc0000082 202 #define MSR_K6_UWCCR 0xc0000085 203 #define MSR_K6_EPMR 0xc0000086 204 #define MSR_K6_PSOR 0xc0000087 205 #define MSR_K6_PFIR 0xc0000088 206 207 /* Centaur-Hauls/IDT defined MSRs. */ 208 #define MSR_IDT_FCR1 0x00000107 209 #define MSR_IDT_FCR2 0x00000108 210 #define MSR_IDT_FCR3 0x00000109 211 #define MSR_IDT_FCR4 0x0000010a 212 213 #define MSR_IDT_MCR0 0x00000110 214 #define MSR_IDT_MCR1 0x00000111 215 #define MSR_IDT_MCR2 0x00000112 216 #define MSR_IDT_MCR3 0x00000113 217 #define MSR_IDT_MCR4 0x00000114 218 #define MSR_IDT_MCR5 0x00000115 219 #define MSR_IDT_MCR6 0x00000116 220 #define MSR_IDT_MCR7 0x00000117 221 #define MSR_IDT_MCR_CTRL 0x00000120 222 223 /* VIA Cyrix defined MSRs*/ 224 #define MSR_VIA_FCR 0x00001107 225 #define MSR_VIA_LONGHAUL 0x0000110a 226 #define MSR_VIA_RNG 0x0000110b 227 #define MSR_VIA_BCR2 0x00001147 228 229 /* Transmeta defined MSRs */ 230 #define MSR_TMTA_LONGRUN_CTRL 0x80868010 231 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 232 #define MSR_TMTA_LRTI_READOUT 0x80868018 233 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 234 235 /* Intel defined MSRs. */ 236 #define MSR_IA32_P5_MC_ADDR 0x00000000 237 #define MSR_IA32_P5_MC_TYPE 0x00000001 238 #define MSR_IA32_TSC 0x00000010 239 #define MSR_IA32_PLATFORM_ID 0x00000017 240 #define MSR_IA32_EBL_CR_POWERON 0x0000002a 241 #define MSR_EBC_FREQUENCY_ID 0x0000002c 242 #define MSR_IA32_FEATURE_CONTROL 0x0000003a 243 244 #define FEATURE_CONTROL_LOCKED (1<<0) 245 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) 246 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 247 248 #define MSR_IA32_APICBASE 0x0000001b 249 #define MSR_IA32_APICBASE_BSP (1<<8) 250 #define MSR_IA32_APICBASE_ENABLE (1<<11) 251 #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 252 253 #define MSR_IA32_UCODE_WRITE 0x00000079 254 #define MSR_IA32_UCODE_REV 0x0000008b 255 256 #define MSR_IA32_PERF_STATUS 0x00000198 257 #define MSR_IA32_PERF_CTL 0x00000199 258 259 #define MSR_IA32_MPERF 0x000000e7 260 #define MSR_IA32_APERF 0x000000e8 261 262 #define MSR_IA32_THERM_CONTROL 0x0000019a 263 #define MSR_IA32_THERM_INTERRUPT 0x0000019b 264 265 #define THERM_INT_HIGH_ENABLE (1 << 0) 266 #define THERM_INT_LOW_ENABLE (1 << 1) 267 #define THERM_INT_PLN_ENABLE (1 << 24) 268 269 #define MSR_IA32_THERM_STATUS 0x0000019c 270 271 #define THERM_STATUS_PROCHOT (1 << 0) 272 #define THERM_STATUS_POWER_LIMIT (1 << 10) 273 274 #define MSR_THERM2_CTL 0x0000019d 275 276 #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 277 278 #define MSR_IA32_MISC_ENABLE 0x000001a0 279 280 #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 281 282 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 283 284 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 285 286 #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 287 #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 288 289 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 290 291 #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 292 #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 293 #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 294 295 /* Thermal Thresholds Support */ 296 #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 297 #define THERM_SHIFT_THRESHOLD0 8 298 #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 299 #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 300 #define THERM_SHIFT_THRESHOLD1 16 301 #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 302 #define THERM_STATUS_THRESHOLD0 (1 << 6) 303 #define THERM_LOG_THRESHOLD0 (1 << 7) 304 #define THERM_STATUS_THRESHOLD1 (1 << 8) 305 #define THERM_LOG_THRESHOLD1 (1 << 9) 306 307 /* MISC_ENABLE bits: architectural */ 308 #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0) 309 #define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1) 310 #define MSR_IA32_MISC_ENABLE_EMON (1ULL << 7) 311 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11) 312 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12) 313 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16) 314 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) 315 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << 22) 316 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << 23) 317 #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34) 318 319 /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 320 #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << 2) 321 #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << 3) 322 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4) 323 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << 6) 324 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << 8) 325 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << 9) 326 #define MSR_IA32_MISC_ENABLE_FERR (1ULL << 10) 327 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << 10) 328 #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << 13) 329 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << 19) 330 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << 20) 331 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << 24) 332 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << 37) 333 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38) 334 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39) 335 336 /* P4/Xeon+ specific */ 337 #define MSR_IA32_MCG_EAX 0x00000180 338 #define MSR_IA32_MCG_EBX 0x00000181 339 #define MSR_IA32_MCG_ECX 0x00000182 340 #define MSR_IA32_MCG_EDX 0x00000183 341 #define MSR_IA32_MCG_ESI 0x00000184 342 #define MSR_IA32_MCG_EDI 0x00000185 343 #define MSR_IA32_MCG_EBP 0x00000186 344 #define MSR_IA32_MCG_ESP 0x00000187 345 #define MSR_IA32_MCG_EFLAGS 0x00000188 346 #define MSR_IA32_MCG_EIP 0x00000189 347 #define MSR_IA32_MCG_RESERVED 0x0000018a 348 349 /* Pentium IV performance counter MSRs */ 350 #define MSR_P4_BPU_PERFCTR0 0x00000300 351 #define MSR_P4_BPU_PERFCTR1 0x00000301 352 #define MSR_P4_BPU_PERFCTR2 0x00000302 353 #define MSR_P4_BPU_PERFCTR3 0x00000303 354 #define MSR_P4_MS_PERFCTR0 0x00000304 355 #define MSR_P4_MS_PERFCTR1 0x00000305 356 #define MSR_P4_MS_PERFCTR2 0x00000306 357 #define MSR_P4_MS_PERFCTR3 0x00000307 358 #define MSR_P4_FLAME_PERFCTR0 0x00000308 359 #define MSR_P4_FLAME_PERFCTR1 0x00000309 360 #define MSR_P4_FLAME_PERFCTR2 0x0000030a 361 #define MSR_P4_FLAME_PERFCTR3 0x0000030b 362 #define MSR_P4_IQ_PERFCTR0 0x0000030c 363 #define MSR_P4_IQ_PERFCTR1 0x0000030d 364 #define MSR_P4_IQ_PERFCTR2 0x0000030e 365 #define MSR_P4_IQ_PERFCTR3 0x0000030f 366 #define MSR_P4_IQ_PERFCTR4 0x00000310 367 #define MSR_P4_IQ_PERFCTR5 0x00000311 368 #define MSR_P4_BPU_CCCR0 0x00000360 369 #define MSR_P4_BPU_CCCR1 0x00000361 370 #define MSR_P4_BPU_CCCR2 0x00000362 371 #define MSR_P4_BPU_CCCR3 0x00000363 372 #define MSR_P4_MS_CCCR0 0x00000364 373 #define MSR_P4_MS_CCCR1 0x00000365 374 #define MSR_P4_MS_CCCR2 0x00000366 375 #define MSR_P4_MS_CCCR3 0x00000367 376 #define MSR_P4_FLAME_CCCR0 0x00000368 377 #define MSR_P4_FLAME_CCCR1 0x00000369 378 #define MSR_P4_FLAME_CCCR2 0x0000036a 379 #define MSR_P4_FLAME_CCCR3 0x0000036b 380 #define MSR_P4_IQ_CCCR0 0x0000036c 381 #define MSR_P4_IQ_CCCR1 0x0000036d 382 #define MSR_P4_IQ_CCCR2 0x0000036e 383 #define MSR_P4_IQ_CCCR3 0x0000036f 384 #define MSR_P4_IQ_CCCR4 0x00000370 385 #define MSR_P4_IQ_CCCR5 0x00000371 386 #define MSR_P4_ALF_ESCR0 0x000003ca 387 #define MSR_P4_ALF_ESCR1 0x000003cb 388 #define MSR_P4_BPU_ESCR0 0x000003b2 389 #define MSR_P4_BPU_ESCR1 0x000003b3 390 #define MSR_P4_BSU_ESCR0 0x000003a0 391 #define MSR_P4_BSU_ESCR1 0x000003a1 392 #define MSR_P4_CRU_ESCR0 0x000003b8 393 #define MSR_P4_CRU_ESCR1 0x000003b9 394 #define MSR_P4_CRU_ESCR2 0x000003cc 395 #define MSR_P4_CRU_ESCR3 0x000003cd 396 #define MSR_P4_CRU_ESCR4 0x000003e0 397 #define MSR_P4_CRU_ESCR5 0x000003e1 398 #define MSR_P4_DAC_ESCR0 0x000003a8 399 #define MSR_P4_DAC_ESCR1 0x000003a9 400 #define MSR_P4_FIRM_ESCR0 0x000003a4 401 #define MSR_P4_FIRM_ESCR1 0x000003a5 402 #define MSR_P4_FLAME_ESCR0 0x000003a6 403 #define MSR_P4_FLAME_ESCR1 0x000003a7 404 #define MSR_P4_FSB_ESCR0 0x000003a2 405 #define MSR_P4_FSB_ESCR1 0x000003a3 406 #define MSR_P4_IQ_ESCR0 0x000003ba 407 #define MSR_P4_IQ_ESCR1 0x000003bb 408 #define MSR_P4_IS_ESCR0 0x000003b4 409 #define MSR_P4_IS_ESCR1 0x000003b5 410 #define MSR_P4_ITLB_ESCR0 0x000003b6 411 #define MSR_P4_ITLB_ESCR1 0x000003b7 412 #define MSR_P4_IX_ESCR0 0x000003c8 413 #define MSR_P4_IX_ESCR1 0x000003c9 414 #define MSR_P4_MOB_ESCR0 0x000003aa 415 #define MSR_P4_MOB_ESCR1 0x000003ab 416 #define MSR_P4_MS_ESCR0 0x000003c0 417 #define MSR_P4_MS_ESCR1 0x000003c1 418 #define MSR_P4_PMH_ESCR0 0x000003ac 419 #define MSR_P4_PMH_ESCR1 0x000003ad 420 #define MSR_P4_RAT_ESCR0 0x000003bc 421 #define MSR_P4_RAT_ESCR1 0x000003bd 422 #define MSR_P4_SAAT_ESCR0 0x000003ae 423 #define MSR_P4_SAAT_ESCR1 0x000003af 424 #define MSR_P4_SSU_ESCR0 0x000003be 425 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 426 427 #define MSR_P4_TBPU_ESCR0 0x000003c2 428 #define MSR_P4_TBPU_ESCR1 0x000003c3 429 #define MSR_P4_TC_ESCR0 0x000003c4 430 #define MSR_P4_TC_ESCR1 0x000003c5 431 #define MSR_P4_U2L_ESCR0 0x000003b0 432 #define MSR_P4_U2L_ESCR1 0x000003b1 433 434 #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 435 436 /* Intel Core-based CPU performance counters */ 437 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 438 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 439 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 440 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 441 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 442 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 443 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 444 445 /* Geode defined MSRs */ 446 #define MSR_GEODE_BUSCONT_CONF0 0x00001900 447 448 /* Intel VT MSRs */ 449 #define MSR_IA32_VMX_BASIC 0x00000480 450 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 451 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 452 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 453 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 454 #define MSR_IA32_VMX_MISC 0x00000485 455 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 456 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 457 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 458 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 459 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 460 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 461 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 462 463 /* AMD-V MSRs */ 464 465 #define MSR_VM_CR 0xc0010114 466 #define MSR_VM_IGNNE 0xc0010115 467 #define MSR_VM_HSAVE_PA 0xc0010117 468 469 #endif /* _ASM_X86_MSR_INDEX_H */ 470