1 /* 2 * Taken from the linux kernel file of the same name 3 * 4 * (C) Copyright 2012 5 * Graeme Russ, <graeme.russ@gmail.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _ASM_X86_MSR_INDEX_H 11 #define _ASM_X86_MSR_INDEX_H 12 13 /* CPU model specific register (MSR) numbers */ 14 15 /* x86-64 specific MSRs */ 16 #define MSR_EFER 0xc0000080 /* extended feature register */ 17 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 18 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 19 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 20 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 21 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 22 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 23 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 24 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 25 26 /* EFER bits: */ 27 #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 28 #define _EFER_LME 8 /* Long mode enable */ 29 #define _EFER_LMA 10 /* Long mode active (read-only) */ 30 #define _EFER_NX 11 /* No execute enable */ 31 #define _EFER_SVME 12 /* Enable virtualization */ 32 #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 33 #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 34 35 #define EFER_SCE (1<<_EFER_SCE) 36 #define EFER_LME (1<<_EFER_LME) 37 #define EFER_LMA (1<<_EFER_LMA) 38 #define EFER_NX (1<<_EFER_NX) 39 #define EFER_SVME (1<<_EFER_SVME) 40 #define EFER_LMSLE (1<<_EFER_LMSLE) 41 #define EFER_FFXSR (1<<_EFER_FFXSR) 42 43 /* Intel MSRs. Some also available on other CPUs */ 44 #define MSR_IA32_PERFCTR0 0x000000c1 45 #define MSR_IA32_PERFCTR1 0x000000c2 46 #define MSR_FSB_FREQ 0x000000cd 47 #define MSR_NHM_PLATFORM_INFO 0x000000ce 48 49 #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 50 #define NHM_C3_AUTO_DEMOTE (1UL << 25) 51 #define NHM_C1_AUTO_DEMOTE (1UL << 26) 52 #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 53 #define SNB_C1_AUTO_UNDEMOTE (1UL << 27) 54 #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) 55 56 #define MSR_PLATFORM_INFO 0x000000ce 57 #define MSR_MTRRcap 0x000000fe 58 #define MSR_IA32_BBL_CR_CTL 0x00000119 59 #define MSR_IA32_BBL_CR_CTL3 0x0000011e 60 61 #define MSR_IA32_SYSENTER_CS 0x00000174 62 #define MSR_IA32_SYSENTER_ESP 0x00000175 63 #define MSR_IA32_SYSENTER_EIP 0x00000176 64 65 #define MSR_IA32_MCG_CAP 0x00000179 66 #define MSR_IA32_MCG_STATUS 0x0000017a 67 #define MSR_IA32_MCG_CTL 0x0000017b 68 69 #define MSR_OFFCORE_RSP_0 0x000001a6 70 #define MSR_OFFCORE_RSP_1 0x000001a7 71 #define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad 72 #define MSR_IVT_TURBO_RATIO_LIMIT 0x000001ae 73 74 #define MSR_LBR_SELECT 0x000001c8 75 #define MSR_LBR_TOS 0x000001c9 76 #define MSR_LBR_NHM_FROM 0x00000680 77 #define MSR_LBR_NHM_TO 0x000006c0 78 #define MSR_LBR_CORE_FROM 0x00000040 79 #define MSR_LBR_CORE_TO 0x00000060 80 81 #define MSR_IA32_PEBS_ENABLE 0x000003f1 82 #define MSR_IA32_DS_AREA 0x00000600 83 #define MSR_IA32_PERF_CAPABILITIES 0x00000345 84 #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 85 86 #define MSR_MTRRfix64K_00000 0x00000250 87 #define MSR_MTRRfix16K_80000 0x00000258 88 #define MSR_MTRRfix16K_A0000 0x00000259 89 #define MSR_MTRRfix4K_C0000 0x00000268 90 #define MSR_MTRRfix4K_C8000 0x00000269 91 #define MSR_MTRRfix4K_D0000 0x0000026a 92 #define MSR_MTRRfix4K_D8000 0x0000026b 93 #define MSR_MTRRfix4K_E0000 0x0000026c 94 #define MSR_MTRRfix4K_E8000 0x0000026d 95 #define MSR_MTRRfix4K_F0000 0x0000026e 96 #define MSR_MTRRfix4K_F8000 0x0000026f 97 #define MSR_MTRRdefType 0x000002ff 98 99 #define MSR_IA32_CR_PAT 0x00000277 100 101 #define MSR_IA32_DEBUGCTLMSR 0x000001d9 102 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 103 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 104 #define MSR_IA32_LASTINTFROMIP 0x000001dd 105 #define MSR_IA32_LASTINTTOIP 0x000001de 106 107 /* DEBUGCTLMSR bits (others vary by model): */ 108 #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 109 /* single-step on branches */ 110 #define DEBUGCTLMSR_BTF (1UL << 1) 111 #define DEBUGCTLMSR_TR (1UL << 6) 112 #define DEBUGCTLMSR_BTS (1UL << 7) 113 #define DEBUGCTLMSR_BTINT (1UL << 8) 114 #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 115 #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 116 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 117 118 #define MSR_IA32_POWER_CTL 0x000001fc 119 120 #define MSR_IA32_MC0_CTL 0x00000400 121 #define MSR_IA32_MC0_STATUS 0x00000401 122 #define MSR_IA32_MC0_ADDR 0x00000402 123 #define MSR_IA32_MC0_MISC 0x00000403 124 125 /* C-state Residency Counters */ 126 #define MSR_PKG_C3_RESIDENCY 0x000003f8 127 #define MSR_PKG_C6_RESIDENCY 0x000003f9 128 #define MSR_PKG_C7_RESIDENCY 0x000003fa 129 #define MSR_CORE_C3_RESIDENCY 0x000003fc 130 #define MSR_CORE_C6_RESIDENCY 0x000003fd 131 #define MSR_CORE_C7_RESIDENCY 0x000003fe 132 #define MSR_PKG_C2_RESIDENCY 0x0000060d 133 #define MSR_PKG_C8_RESIDENCY 0x00000630 134 #define MSR_PKG_C9_RESIDENCY 0x00000631 135 #define MSR_PKG_C10_RESIDENCY 0x00000632 136 137 /* Run Time Average Power Limiting (RAPL) Interface */ 138 139 #define MSR_RAPL_POWER_UNIT 0x00000606 140 141 #define MSR_PKG_POWER_LIMIT 0x00000610 142 #define MSR_PKG_ENERGY_STATUS 0x00000611 143 #define MSR_PKG_PERF_STATUS 0x00000613 144 #define MSR_PKG_POWER_INFO 0x00000614 145 146 #define MSR_DRAM_POWER_LIMIT 0x00000618 147 #define MSR_DRAM_ENERGY_STATUS 0x00000619 148 #define MSR_DRAM_PERF_STATUS 0x0000061b 149 #define MSR_DRAM_POWER_INFO 0x0000061c 150 151 #define MSR_PP0_POWER_LIMIT 0x00000638 152 #define MSR_PP0_ENERGY_STATUS 0x00000639 153 #define MSR_PP0_POLICY 0x0000063a 154 #define MSR_PP0_PERF_STATUS 0x0000063b 155 156 #define MSR_PP1_POWER_LIMIT 0x00000640 157 #define MSR_PP1_ENERGY_STATUS 0x00000641 158 #define MSR_PP1_POLICY 0x00000642 159 160 #define MSR_CORE_C1_RES 0x00000660 161 162 #define MSR_AMD64_MC0_MASK 0xc0010044 163 164 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 165 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 166 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 167 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 168 169 #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 170 171 /* These are consecutive and not in the normal 4er MCE bank block */ 172 #define MSR_IA32_MC0_CTL2 0x00000280 173 #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 174 175 #define MSR_P6_PERFCTR0 0x000000c1 176 #define MSR_P6_PERFCTR1 0x000000c2 177 #define MSR_P6_EVNTSEL0 0x00000186 178 #define MSR_P6_EVNTSEL1 0x00000187 179 180 #define MSR_KNC_PERFCTR0 0x00000020 181 #define MSR_KNC_PERFCTR1 0x00000021 182 #define MSR_KNC_EVNTSEL0 0x00000028 183 #define MSR_KNC_EVNTSEL1 0x00000029 184 185 /* Alternative perfctr range with full access. */ 186 #define MSR_IA32_PMC0 0x000004c1 187 188 /* AMD64 MSRs. Not complete. See the architecture manual for a more 189 complete list. */ 190 191 #define MSR_AMD64_PATCH_LEVEL 0x0000008b 192 #define MSR_AMD64_TSC_RATIO 0xc0000104 193 #define MSR_AMD64_NB_CFG 0xc001001f 194 #define MSR_AMD64_PATCH_LOADER 0xc0010020 195 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 196 #define MSR_AMD64_OSVW_STATUS 0xc0010141 197 #define MSR_AMD64_LS_CFG 0xc0011020 198 #define MSR_AMD64_DC_CFG 0xc0011022 199 #define MSR_AMD64_BU_CFG2 0xc001102a 200 #define MSR_AMD64_IBSFETCHCTL 0xc0011030 201 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 202 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 203 #define MSR_AMD64_IBSFETCH_REG_COUNT 3 204 #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 205 #define MSR_AMD64_IBSOPCTL 0xc0011033 206 #define MSR_AMD64_IBSOPRIP 0xc0011034 207 #define MSR_AMD64_IBSOPDATA 0xc0011035 208 #define MSR_AMD64_IBSOPDATA2 0xc0011036 209 #define MSR_AMD64_IBSOPDATA3 0xc0011037 210 #define MSR_AMD64_IBSDCLINAD 0xc0011038 211 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 212 #define MSR_AMD64_IBSOP_REG_COUNT 7 213 #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 214 #define MSR_AMD64_IBSCTL 0xc001103a 215 #define MSR_AMD64_IBSBRTARGET 0xc001103b 216 #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 217 218 /* Fam 16h MSRs */ 219 #define MSR_F16H_L2I_PERF_CTL 0xc0010230 220 #define MSR_F16H_L2I_PERF_CTR 0xc0010231 221 222 /* Fam 15h MSRs */ 223 #define MSR_F15H_PERF_CTL 0xc0010200 224 #define MSR_F15H_PERF_CTR 0xc0010201 225 #define MSR_F15H_NB_PERF_CTL 0xc0010240 226 #define MSR_F15H_NB_PERF_CTR 0xc0010241 227 228 /* Fam 10h MSRs */ 229 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 230 #define FAM10H_MMIO_CONF_ENABLE (1<<0) 231 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 232 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 233 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 234 #define FAM10H_MMIO_CONF_BASE_SHIFT 20 235 #define MSR_FAM10H_NODE_ID 0xc001100c 236 237 /* K8 MSRs */ 238 #define MSR_K8_TOP_MEM1 0xc001001a 239 #define MSR_K8_TOP_MEM2 0xc001001d 240 #define MSR_K8_SYSCFG 0xc0010010 241 #define MSR_K8_INT_PENDING_MSG 0xc0010055 242 /* C1E active bits in int pending message */ 243 #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 244 #define MSR_K8_TSEG_ADDR 0xc0010112 245 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 246 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 247 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 248 249 /* K7 MSRs */ 250 #define MSR_K7_EVNTSEL0 0xc0010000 251 #define MSR_K7_PERFCTR0 0xc0010004 252 #define MSR_K7_EVNTSEL1 0xc0010001 253 #define MSR_K7_PERFCTR1 0xc0010005 254 #define MSR_K7_EVNTSEL2 0xc0010002 255 #define MSR_K7_PERFCTR2 0xc0010006 256 #define MSR_K7_EVNTSEL3 0xc0010003 257 #define MSR_K7_PERFCTR3 0xc0010007 258 #define MSR_K7_CLK_CTL 0xc001001b 259 #define MSR_K7_HWCR 0xc0010015 260 #define MSR_K7_FID_VID_CTL 0xc0010041 261 #define MSR_K7_FID_VID_STATUS 0xc0010042 262 263 /* K6 MSRs */ 264 #define MSR_K6_WHCR 0xc0000082 265 #define MSR_K6_UWCCR 0xc0000085 266 #define MSR_K6_EPMR 0xc0000086 267 #define MSR_K6_PSOR 0xc0000087 268 #define MSR_K6_PFIR 0xc0000088 269 270 /* Centaur-Hauls/IDT defined MSRs. */ 271 #define MSR_IDT_FCR1 0x00000107 272 #define MSR_IDT_FCR2 0x00000108 273 #define MSR_IDT_FCR3 0x00000109 274 #define MSR_IDT_FCR4 0x0000010a 275 276 #define MSR_IDT_MCR0 0x00000110 277 #define MSR_IDT_MCR1 0x00000111 278 #define MSR_IDT_MCR2 0x00000112 279 #define MSR_IDT_MCR3 0x00000113 280 #define MSR_IDT_MCR4 0x00000114 281 #define MSR_IDT_MCR5 0x00000115 282 #define MSR_IDT_MCR6 0x00000116 283 #define MSR_IDT_MCR7 0x00000117 284 #define MSR_IDT_MCR_CTRL 0x00000120 285 286 /* VIA Cyrix defined MSRs*/ 287 #define MSR_VIA_FCR 0x00001107 288 #define MSR_VIA_LONGHAUL 0x0000110a 289 #define MSR_VIA_RNG 0x0000110b 290 #define MSR_VIA_BCR2 0x00001147 291 292 /* Transmeta defined MSRs */ 293 #define MSR_TMTA_LONGRUN_CTRL 0x80868010 294 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 295 #define MSR_TMTA_LRTI_READOUT 0x80868018 296 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 297 298 /* Intel defined MSRs. */ 299 #define MSR_IA32_P5_MC_ADDR 0x00000000 300 #define MSR_IA32_P5_MC_TYPE 0x00000001 301 #define MSR_IA32_TSC 0x00000010 302 #define MSR_IA32_PLATFORM_ID 0x00000017 303 #define MSR_IA32_EBL_CR_POWERON 0x0000002a 304 #define MSR_EBC_FREQUENCY_ID 0x0000002c 305 #define MSR_SMI_COUNT 0x00000034 306 #define MSR_IA32_FEATURE_CONTROL 0x0000003a 307 #define MSR_IA32_TSC_ADJUST 0x0000003b 308 309 #define FEATURE_CONTROL_LOCKED (1<<0) 310 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) 311 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 312 313 #define MSR_IA32_APICBASE 0x0000001b 314 #define MSR_IA32_APICBASE_BSP (1<<8) 315 #define MSR_IA32_APICBASE_ENABLE (1<<11) 316 #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 317 318 #define MSR_IA32_TSCDEADLINE 0x000006e0 319 320 #define MSR_IA32_UCODE_WRITE 0x00000079 321 #define MSR_IA32_UCODE_REV 0x0000008b 322 323 #define MSR_IA32_PERF_STATUS 0x00000198 324 #define MSR_IA32_PERF_CTL 0x00000199 325 #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 326 #define MSR_AMD_PERF_STATUS 0xc0010063 327 #define MSR_AMD_PERF_CTL 0xc0010062 328 329 #define MSR_IA32_MPERF 0x000000e7 330 #define MSR_IA32_APERF 0x000000e8 331 332 #define MSR_IA32_THERM_CONTROL 0x0000019a 333 #define MSR_IA32_THERM_INTERRUPT 0x0000019b 334 335 #define THERM_INT_HIGH_ENABLE (1 << 0) 336 #define THERM_INT_LOW_ENABLE (1 << 1) 337 #define THERM_INT_PLN_ENABLE (1 << 24) 338 339 #define MSR_IA32_THERM_STATUS 0x0000019c 340 341 #define THERM_STATUS_PROCHOT (1 << 0) 342 #define THERM_STATUS_POWER_LIMIT (1 << 10) 343 344 #define MSR_THERM2_CTL 0x0000019d 345 346 #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 347 348 #define MSR_IA32_MISC_ENABLE 0x000001a0 349 350 #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 351 352 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 353 #define ENERGY_PERF_BIAS_PERFORMANCE 0 354 #define ENERGY_PERF_BIAS_NORMAL 6 355 #define ENERGY_PERF_BIAS_POWERSAVE 15 356 357 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 358 359 #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 360 #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 361 362 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 363 364 #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 365 #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 366 #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 367 368 /* Thermal Thresholds Support */ 369 #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 370 #define THERM_SHIFT_THRESHOLD0 8 371 #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 372 #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 373 #define THERM_SHIFT_THRESHOLD1 16 374 #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 375 #define THERM_STATUS_THRESHOLD0 (1 << 6) 376 #define THERM_LOG_THRESHOLD0 (1 << 7) 377 #define THERM_STATUS_THRESHOLD1 (1 << 8) 378 #define THERM_LOG_THRESHOLD1 (1 << 9) 379 380 /* MISC_ENABLE bits: architectural */ 381 #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0) 382 #define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1) 383 #define MSR_IA32_MISC_ENABLE_EMON (1ULL << 7) 384 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11) 385 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12) 386 #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16) 387 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) 388 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << 22) 389 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << 23) 390 #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34) 391 392 /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 393 #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << 2) 394 #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << 3) 395 #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4) 396 #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << 6) 397 #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << 8) 398 #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << 9) 399 #define MSR_IA32_MISC_ENABLE_FERR (1ULL << 10) 400 #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << 10) 401 #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << 13) 402 #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << 19) 403 #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << 20) 404 #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << 24) 405 #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << 37) 406 #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38) 407 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39) 408 409 #define MSR_IA32_TSC_DEADLINE 0x000006E0 410 411 /* P4/Xeon+ specific */ 412 #define MSR_IA32_MCG_EAX 0x00000180 413 #define MSR_IA32_MCG_EBX 0x00000181 414 #define MSR_IA32_MCG_ECX 0x00000182 415 #define MSR_IA32_MCG_EDX 0x00000183 416 #define MSR_IA32_MCG_ESI 0x00000184 417 #define MSR_IA32_MCG_EDI 0x00000185 418 #define MSR_IA32_MCG_EBP 0x00000186 419 #define MSR_IA32_MCG_ESP 0x00000187 420 #define MSR_IA32_MCG_EFLAGS 0x00000188 421 #define MSR_IA32_MCG_EIP 0x00000189 422 #define MSR_IA32_MCG_RESERVED 0x0000018a 423 424 /* Pentium IV performance counter MSRs */ 425 #define MSR_P4_BPU_PERFCTR0 0x00000300 426 #define MSR_P4_BPU_PERFCTR1 0x00000301 427 #define MSR_P4_BPU_PERFCTR2 0x00000302 428 #define MSR_P4_BPU_PERFCTR3 0x00000303 429 #define MSR_P4_MS_PERFCTR0 0x00000304 430 #define MSR_P4_MS_PERFCTR1 0x00000305 431 #define MSR_P4_MS_PERFCTR2 0x00000306 432 #define MSR_P4_MS_PERFCTR3 0x00000307 433 #define MSR_P4_FLAME_PERFCTR0 0x00000308 434 #define MSR_P4_FLAME_PERFCTR1 0x00000309 435 #define MSR_P4_FLAME_PERFCTR2 0x0000030a 436 #define MSR_P4_FLAME_PERFCTR3 0x0000030b 437 #define MSR_P4_IQ_PERFCTR0 0x0000030c 438 #define MSR_P4_IQ_PERFCTR1 0x0000030d 439 #define MSR_P4_IQ_PERFCTR2 0x0000030e 440 #define MSR_P4_IQ_PERFCTR3 0x0000030f 441 #define MSR_P4_IQ_PERFCTR4 0x00000310 442 #define MSR_P4_IQ_PERFCTR5 0x00000311 443 #define MSR_P4_BPU_CCCR0 0x00000360 444 #define MSR_P4_BPU_CCCR1 0x00000361 445 #define MSR_P4_BPU_CCCR2 0x00000362 446 #define MSR_P4_BPU_CCCR3 0x00000363 447 #define MSR_P4_MS_CCCR0 0x00000364 448 #define MSR_P4_MS_CCCR1 0x00000365 449 #define MSR_P4_MS_CCCR2 0x00000366 450 #define MSR_P4_MS_CCCR3 0x00000367 451 #define MSR_P4_FLAME_CCCR0 0x00000368 452 #define MSR_P4_FLAME_CCCR1 0x00000369 453 #define MSR_P4_FLAME_CCCR2 0x0000036a 454 #define MSR_P4_FLAME_CCCR3 0x0000036b 455 #define MSR_P4_IQ_CCCR0 0x0000036c 456 #define MSR_P4_IQ_CCCR1 0x0000036d 457 #define MSR_P4_IQ_CCCR2 0x0000036e 458 #define MSR_P4_IQ_CCCR3 0x0000036f 459 #define MSR_P4_IQ_CCCR4 0x00000370 460 #define MSR_P4_IQ_CCCR5 0x00000371 461 #define MSR_P4_ALF_ESCR0 0x000003ca 462 #define MSR_P4_ALF_ESCR1 0x000003cb 463 #define MSR_P4_BPU_ESCR0 0x000003b2 464 #define MSR_P4_BPU_ESCR1 0x000003b3 465 #define MSR_P4_BSU_ESCR0 0x000003a0 466 #define MSR_P4_BSU_ESCR1 0x000003a1 467 #define MSR_P4_CRU_ESCR0 0x000003b8 468 #define MSR_P4_CRU_ESCR1 0x000003b9 469 #define MSR_P4_CRU_ESCR2 0x000003cc 470 #define MSR_P4_CRU_ESCR3 0x000003cd 471 #define MSR_P4_CRU_ESCR4 0x000003e0 472 #define MSR_P4_CRU_ESCR5 0x000003e1 473 #define MSR_P4_DAC_ESCR0 0x000003a8 474 #define MSR_P4_DAC_ESCR1 0x000003a9 475 #define MSR_P4_FIRM_ESCR0 0x000003a4 476 #define MSR_P4_FIRM_ESCR1 0x000003a5 477 #define MSR_P4_FLAME_ESCR0 0x000003a6 478 #define MSR_P4_FLAME_ESCR1 0x000003a7 479 #define MSR_P4_FSB_ESCR0 0x000003a2 480 #define MSR_P4_FSB_ESCR1 0x000003a3 481 #define MSR_P4_IQ_ESCR0 0x000003ba 482 #define MSR_P4_IQ_ESCR1 0x000003bb 483 #define MSR_P4_IS_ESCR0 0x000003b4 484 #define MSR_P4_IS_ESCR1 0x000003b5 485 #define MSR_P4_ITLB_ESCR0 0x000003b6 486 #define MSR_P4_ITLB_ESCR1 0x000003b7 487 #define MSR_P4_IX_ESCR0 0x000003c8 488 #define MSR_P4_IX_ESCR1 0x000003c9 489 #define MSR_P4_MOB_ESCR0 0x000003aa 490 #define MSR_P4_MOB_ESCR1 0x000003ab 491 #define MSR_P4_MS_ESCR0 0x000003c0 492 #define MSR_P4_MS_ESCR1 0x000003c1 493 #define MSR_P4_PMH_ESCR0 0x000003ac 494 #define MSR_P4_PMH_ESCR1 0x000003ad 495 #define MSR_P4_RAT_ESCR0 0x000003bc 496 #define MSR_P4_RAT_ESCR1 0x000003bd 497 #define MSR_P4_SAAT_ESCR0 0x000003ae 498 #define MSR_P4_SAAT_ESCR1 0x000003af 499 #define MSR_P4_SSU_ESCR0 0x000003be 500 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 501 502 #define MSR_P4_TBPU_ESCR0 0x000003c2 503 #define MSR_P4_TBPU_ESCR1 0x000003c3 504 #define MSR_P4_TC_ESCR0 0x000003c4 505 #define MSR_P4_TC_ESCR1 0x000003c5 506 #define MSR_P4_U2L_ESCR0 0x000003b0 507 #define MSR_P4_U2L_ESCR1 0x000003b1 508 509 #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 510 511 /* Intel Core-based CPU performance counters */ 512 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 513 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 514 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 515 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 516 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 517 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 518 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 519 520 /* Geode defined MSRs */ 521 #define MSR_GEODE_BUSCONT_CONF0 0x00001900 522 523 /* Intel VT MSRs */ 524 #define MSR_IA32_VMX_BASIC 0x00000480 525 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 526 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 527 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 528 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 529 #define MSR_IA32_VMX_MISC 0x00000485 530 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 531 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 532 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 533 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 534 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 535 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 536 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 537 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 538 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 539 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 540 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 541 #define MSR_IA32_VMX_VMFUNC 0x00000491 542 543 /* VMX_BASIC bits and bitmasks */ 544 #define VMX_BASIC_VMCS_SIZE_SHIFT 32 545 #define VMX_BASIC_64 0x0001000000000000LLU 546 #define VMX_BASIC_MEM_TYPE_SHIFT 50 547 #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 548 #define VMX_BASIC_MEM_TYPE_WB 6LLU 549 #define VMX_BASIC_INOUT 0x0040000000000000LLU 550 551 /* MSR_IA32_VMX_MISC bits */ 552 #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 553 #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 554 /* AMD-V MSRs */ 555 556 #define MSR_VM_CR 0xc0010114 557 #define MSR_VM_IGNNE 0xc0010115 558 #define MSR_VM_HSAVE_PA 0xc0010117 559 560 #endif /* _ASM_X86_MSR_INDEX_H */ 561