198568f0fSGraeme Russ /* 298568f0fSGraeme Russ * Taken from the linux kernel file of the same name 398568f0fSGraeme Russ * 498568f0fSGraeme Russ * (C) Copyright 2012 598568f0fSGraeme Russ * Graeme Russ, <graeme.russ@gmail.com> 698568f0fSGraeme Russ * 71a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 898568f0fSGraeme Russ */ 998568f0fSGraeme Russ 1098568f0fSGraeme Russ #ifndef _ASM_X86_MSR_INDEX_H 1198568f0fSGraeme Russ #define _ASM_X86_MSR_INDEX_H 1298568f0fSGraeme Russ 1398568f0fSGraeme Russ /* CPU model specific register (MSR) numbers */ 1498568f0fSGraeme Russ 1598568f0fSGraeme Russ /* x86-64 specific MSRs */ 1698568f0fSGraeme Russ #define MSR_EFER 0xc0000080 /* extended feature register */ 1798568f0fSGraeme Russ #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 1898568f0fSGraeme Russ #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 1998568f0fSGraeme Russ #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 2098568f0fSGraeme Russ #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 2198568f0fSGraeme Russ #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 2298568f0fSGraeme Russ #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 2398568f0fSGraeme Russ #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 2498568f0fSGraeme Russ #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 2598568f0fSGraeme Russ 2698568f0fSGraeme Russ /* EFER bits: */ 2798568f0fSGraeme Russ #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 2898568f0fSGraeme Russ #define _EFER_LME 8 /* Long mode enable */ 2998568f0fSGraeme Russ #define _EFER_LMA 10 /* Long mode active (read-only) */ 3098568f0fSGraeme Russ #define _EFER_NX 11 /* No execute enable */ 3198568f0fSGraeme Russ #define _EFER_SVME 12 /* Enable virtualization */ 3298568f0fSGraeme Russ #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 3398568f0fSGraeme Russ #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 3498568f0fSGraeme Russ 3598568f0fSGraeme Russ #define EFER_SCE (1<<_EFER_SCE) 3698568f0fSGraeme Russ #define EFER_LME (1<<_EFER_LME) 3798568f0fSGraeme Russ #define EFER_LMA (1<<_EFER_LMA) 3898568f0fSGraeme Russ #define EFER_NX (1<<_EFER_NX) 3998568f0fSGraeme Russ #define EFER_SVME (1<<_EFER_SVME) 4098568f0fSGraeme Russ #define EFER_LMSLE (1<<_EFER_LMSLE) 4198568f0fSGraeme Russ #define EFER_FFXSR (1<<_EFER_FFXSR) 4298568f0fSGraeme Russ 4398568f0fSGraeme Russ /* Intel MSRs. Some also available on other CPUs */ 4498568f0fSGraeme Russ #define MSR_IA32_PERFCTR0 0x000000c1 4598568f0fSGraeme Russ #define MSR_IA32_PERFCTR1 0x000000c2 4698568f0fSGraeme Russ #define MSR_FSB_FREQ 0x000000cd 47dc68584bSSimon Glass #define MSR_NHM_PLATFORM_INFO 0x000000ce 4898568f0fSGraeme Russ 4998568f0fSGraeme Russ #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 5098568f0fSGraeme Russ #define NHM_C3_AUTO_DEMOTE (1UL << 25) 5198568f0fSGraeme Russ #define NHM_C1_AUTO_DEMOTE (1UL << 26) 5298568f0fSGraeme Russ #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 53dc68584bSSimon Glass #define SNB_C1_AUTO_UNDEMOTE (1UL << 27) 54dc68584bSSimon Glass #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) 5598568f0fSGraeme Russ 56*ede97093SSimon Glass #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0x000000cd 57dc68584bSSimon Glass #define MSR_PLATFORM_INFO 0x000000ce 58*ede97093SSimon Glass #define MSR_PMG_CST_CONFIG_CONTROL 0x000000e2 59*ede97093SSimon Glass #define SINGLE_PCTL (1 << 11) 60*ede97093SSimon Glass 6198568f0fSGraeme Russ #define MSR_MTRRcap 0x000000fe 6298568f0fSGraeme Russ #define MSR_IA32_BBL_CR_CTL 0x00000119 6398568f0fSGraeme Russ #define MSR_IA32_BBL_CR_CTL3 0x0000011e 64*ede97093SSimon Glass #define MSR_POWER_MISC 0x00000120 65*ede97093SSimon Glass #define ENABLE_ULFM_AUTOCM_MASK (1 << 2) 66*ede97093SSimon Glass #define ENABLE_INDP_AUTOCM_MASK (1 << 3) 6798568f0fSGraeme Russ 6898568f0fSGraeme Russ #define MSR_IA32_SYSENTER_CS 0x00000174 6998568f0fSGraeme Russ #define MSR_IA32_SYSENTER_ESP 0x00000175 7098568f0fSGraeme Russ #define MSR_IA32_SYSENTER_EIP 0x00000176 7198568f0fSGraeme Russ 7298568f0fSGraeme Russ #define MSR_IA32_MCG_CAP 0x00000179 7398568f0fSGraeme Russ #define MSR_IA32_MCG_STATUS 0x0000017a 7498568f0fSGraeme Russ #define MSR_IA32_MCG_CTL 0x0000017b 7598568f0fSGraeme Russ 76*ede97093SSimon Glass #define MSR_IA32_MISC_ENABLES 0x000001a0 7798568f0fSGraeme Russ #define MSR_OFFCORE_RSP_0 0x000001a6 7898568f0fSGraeme Russ #define MSR_OFFCORE_RSP_1 0x000001a7 79dc68584bSSimon Glass #define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad 80dc68584bSSimon Glass #define MSR_IVT_TURBO_RATIO_LIMIT 0x000001ae 81dc68584bSSimon Glass 82dc68584bSSimon Glass #define MSR_LBR_SELECT 0x000001c8 83dc68584bSSimon Glass #define MSR_LBR_TOS 0x000001c9 84*ede97093SSimon Glass #define MSR_POWER_CTL 0x000001fc 85dc68584bSSimon Glass #define MSR_LBR_NHM_FROM 0x00000680 86dc68584bSSimon Glass #define MSR_LBR_NHM_TO 0x000006c0 87dc68584bSSimon Glass #define MSR_LBR_CORE_FROM 0x00000040 88dc68584bSSimon Glass #define MSR_LBR_CORE_TO 0x00000060 8998568f0fSGraeme Russ 9098568f0fSGraeme Russ #define MSR_IA32_PEBS_ENABLE 0x000003f1 9198568f0fSGraeme Russ #define MSR_IA32_DS_AREA 0x00000600 9298568f0fSGraeme Russ #define MSR_IA32_PERF_CAPABILITIES 0x00000345 93dc68584bSSimon Glass #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 9498568f0fSGraeme Russ 9598568f0fSGraeme Russ #define MSR_MTRRfix64K_00000 0x00000250 9698568f0fSGraeme Russ #define MSR_MTRRfix16K_80000 0x00000258 9798568f0fSGraeme Russ #define MSR_MTRRfix16K_A0000 0x00000259 9898568f0fSGraeme Russ #define MSR_MTRRfix4K_C0000 0x00000268 9998568f0fSGraeme Russ #define MSR_MTRRfix4K_C8000 0x00000269 10098568f0fSGraeme Russ #define MSR_MTRRfix4K_D0000 0x0000026a 10198568f0fSGraeme Russ #define MSR_MTRRfix4K_D8000 0x0000026b 10298568f0fSGraeme Russ #define MSR_MTRRfix4K_E0000 0x0000026c 10398568f0fSGraeme Russ #define MSR_MTRRfix4K_E8000 0x0000026d 10498568f0fSGraeme Russ #define MSR_MTRRfix4K_F0000 0x0000026e 10598568f0fSGraeme Russ #define MSR_MTRRfix4K_F8000 0x0000026f 10698568f0fSGraeme Russ #define MSR_MTRRdefType 0x000002ff 10798568f0fSGraeme Russ 10898568f0fSGraeme Russ #define MSR_IA32_CR_PAT 0x00000277 10998568f0fSGraeme Russ 11098568f0fSGraeme Russ #define MSR_IA32_DEBUGCTLMSR 0x000001d9 11198568f0fSGraeme Russ #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 11298568f0fSGraeme Russ #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 11398568f0fSGraeme Russ #define MSR_IA32_LASTINTFROMIP 0x000001dd 11498568f0fSGraeme Russ #define MSR_IA32_LASTINTTOIP 0x000001de 11598568f0fSGraeme Russ 11698568f0fSGraeme Russ /* DEBUGCTLMSR bits (others vary by model): */ 117dc68584bSSimon Glass #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 118dc68584bSSimon Glass /* single-step on branches */ 11998568f0fSGraeme Russ #define DEBUGCTLMSR_BTF (1UL << 1) 12098568f0fSGraeme Russ #define DEBUGCTLMSR_TR (1UL << 6) 12198568f0fSGraeme Russ #define DEBUGCTLMSR_BTS (1UL << 7) 12298568f0fSGraeme Russ #define DEBUGCTLMSR_BTINT (1UL << 8) 12398568f0fSGraeme Russ #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 12498568f0fSGraeme Russ #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 12598568f0fSGraeme Russ #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 12698568f0fSGraeme Russ 127dc68584bSSimon Glass #define MSR_IA32_POWER_CTL 0x000001fc 128dc68584bSSimon Glass 12998568f0fSGraeme Russ #define MSR_IA32_MC0_CTL 0x00000400 13098568f0fSGraeme Russ #define MSR_IA32_MC0_STATUS 0x00000401 13198568f0fSGraeme Russ #define MSR_IA32_MC0_ADDR 0x00000402 13298568f0fSGraeme Russ #define MSR_IA32_MC0_MISC 0x00000403 13398568f0fSGraeme Russ 134dc68584bSSimon Glass /* C-state Residency Counters */ 135dc68584bSSimon Glass #define MSR_PKG_C3_RESIDENCY 0x000003f8 136dc68584bSSimon Glass #define MSR_PKG_C6_RESIDENCY 0x000003f9 137dc68584bSSimon Glass #define MSR_PKG_C7_RESIDENCY 0x000003fa 138dc68584bSSimon Glass #define MSR_CORE_C3_RESIDENCY 0x000003fc 139dc68584bSSimon Glass #define MSR_CORE_C6_RESIDENCY 0x000003fd 140dc68584bSSimon Glass #define MSR_CORE_C7_RESIDENCY 0x000003fe 141dc68584bSSimon Glass #define MSR_PKG_C2_RESIDENCY 0x0000060d 142dc68584bSSimon Glass #define MSR_PKG_C8_RESIDENCY 0x00000630 143dc68584bSSimon Glass #define MSR_PKG_C9_RESIDENCY 0x00000631 144dc68584bSSimon Glass #define MSR_PKG_C10_RESIDENCY 0x00000632 145dc68584bSSimon Glass 146dc68584bSSimon Glass /* Run Time Average Power Limiting (RAPL) Interface */ 147dc68584bSSimon Glass 148*ede97093SSimon Glass #define MSR_PKG_POWER_SKU_UNIT 0x00000606 149dc68584bSSimon Glass 150dc68584bSSimon Glass #define MSR_PKG_POWER_LIMIT 0x00000610 151dc68584bSSimon Glass #define MSR_PKG_ENERGY_STATUS 0x00000611 152dc68584bSSimon Glass #define MSR_PKG_PERF_STATUS 0x00000613 153dc68584bSSimon Glass #define MSR_PKG_POWER_INFO 0x00000614 154dc68584bSSimon Glass 155dc68584bSSimon Glass #define MSR_DRAM_POWER_LIMIT 0x00000618 156dc68584bSSimon Glass #define MSR_DRAM_ENERGY_STATUS 0x00000619 157dc68584bSSimon Glass #define MSR_DRAM_PERF_STATUS 0x0000061b 158dc68584bSSimon Glass #define MSR_DRAM_POWER_INFO 0x0000061c 159dc68584bSSimon Glass 160dc68584bSSimon Glass #define MSR_PP0_POWER_LIMIT 0x00000638 161dc68584bSSimon Glass #define MSR_PP0_ENERGY_STATUS 0x00000639 162dc68584bSSimon Glass #define MSR_PP0_POLICY 0x0000063a 163dc68584bSSimon Glass #define MSR_PP0_PERF_STATUS 0x0000063b 164dc68584bSSimon Glass 165dc68584bSSimon Glass #define MSR_PP1_POWER_LIMIT 0x00000640 166dc68584bSSimon Glass #define MSR_PP1_ENERGY_STATUS 0x00000641 167dc68584bSSimon Glass #define MSR_PP1_POLICY 0x00000642 168dc68584bSSimon Glass 169dc68584bSSimon Glass #define MSR_CORE_C1_RES 0x00000660 170*ede97093SSimon Glass #define MSR_IACORE_RATIOS 0x0000066a 171*ede97093SSimon Glass #define MSR_IACORE_TURBO_RATIOS 0x0000066c 172*ede97093SSimon Glass #define MSR_IACORE_VIDS 0x0000066b 173*ede97093SSimon Glass #define MSR_IACORE_TURBO_VIDS 0x0000066d 174*ede97093SSimon Glass #define MSR_PKG_TURBO_CFG1 0x00000670 175*ede97093SSimon Glass #define MSR_CPU_TURBO_WKLD_CFG1 0x00000671 176*ede97093SSimon Glass #define MSR_CPU_TURBO_WKLD_CFG2 0x00000672 177*ede97093SSimon Glass #define MSR_CPU_THERM_CFG1 0x00000673 178*ede97093SSimon Glass #define MSR_CPU_THERM_CFG2 0x00000674 179*ede97093SSimon Glass #define MSR_CPU_THERM_SENS_CFG 0x00000675 180dc68584bSSimon Glass 18198568f0fSGraeme Russ #define MSR_AMD64_MC0_MASK 0xc0010044 18298568f0fSGraeme Russ 18398568f0fSGraeme Russ #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 18498568f0fSGraeme Russ #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 18598568f0fSGraeme Russ #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 18698568f0fSGraeme Russ #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 18798568f0fSGraeme Russ 18898568f0fSGraeme Russ #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 18998568f0fSGraeme Russ 19098568f0fSGraeme Russ /* These are consecutive and not in the normal 4er MCE bank block */ 19198568f0fSGraeme Russ #define MSR_IA32_MC0_CTL2 0x00000280 19298568f0fSGraeme Russ #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 19398568f0fSGraeme Russ 19498568f0fSGraeme Russ #define MSR_P6_PERFCTR0 0x000000c1 19598568f0fSGraeme Russ #define MSR_P6_PERFCTR1 0x000000c2 19698568f0fSGraeme Russ #define MSR_P6_EVNTSEL0 0x00000186 19798568f0fSGraeme Russ #define MSR_P6_EVNTSEL1 0x00000187 19898568f0fSGraeme Russ 199dc68584bSSimon Glass #define MSR_KNC_PERFCTR0 0x00000020 200dc68584bSSimon Glass #define MSR_KNC_PERFCTR1 0x00000021 201dc68584bSSimon Glass #define MSR_KNC_EVNTSEL0 0x00000028 202dc68584bSSimon Glass #define MSR_KNC_EVNTSEL1 0x00000029 203dc68584bSSimon Glass 204dc68584bSSimon Glass /* Alternative perfctr range with full access. */ 205dc68584bSSimon Glass #define MSR_IA32_PMC0 0x000004c1 206dc68584bSSimon Glass 20798568f0fSGraeme Russ /* AMD64 MSRs. Not complete. See the architecture manual for a more 20898568f0fSGraeme Russ complete list. */ 20998568f0fSGraeme Russ 21098568f0fSGraeme Russ #define MSR_AMD64_PATCH_LEVEL 0x0000008b 211dc68584bSSimon Glass #define MSR_AMD64_TSC_RATIO 0xc0000104 21298568f0fSGraeme Russ #define MSR_AMD64_NB_CFG 0xc001001f 21398568f0fSGraeme Russ #define MSR_AMD64_PATCH_LOADER 0xc0010020 21498568f0fSGraeme Russ #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 21598568f0fSGraeme Russ #define MSR_AMD64_OSVW_STATUS 0xc0010141 216dc68584bSSimon Glass #define MSR_AMD64_LS_CFG 0xc0011020 21798568f0fSGraeme Russ #define MSR_AMD64_DC_CFG 0xc0011022 218dc68584bSSimon Glass #define MSR_AMD64_BU_CFG2 0xc001102a 21998568f0fSGraeme Russ #define MSR_AMD64_IBSFETCHCTL 0xc0011030 22098568f0fSGraeme Russ #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 22198568f0fSGraeme Russ #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 222dc68584bSSimon Glass #define MSR_AMD64_IBSFETCH_REG_COUNT 3 223dc68584bSSimon Glass #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 22498568f0fSGraeme Russ #define MSR_AMD64_IBSOPCTL 0xc0011033 22598568f0fSGraeme Russ #define MSR_AMD64_IBSOPRIP 0xc0011034 22698568f0fSGraeme Russ #define MSR_AMD64_IBSOPDATA 0xc0011035 22798568f0fSGraeme Russ #define MSR_AMD64_IBSOPDATA2 0xc0011036 22898568f0fSGraeme Russ #define MSR_AMD64_IBSOPDATA3 0xc0011037 22998568f0fSGraeme Russ #define MSR_AMD64_IBSDCLINAD 0xc0011038 23098568f0fSGraeme Russ #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 231dc68584bSSimon Glass #define MSR_AMD64_IBSOP_REG_COUNT 7 232dc68584bSSimon Glass #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 23398568f0fSGraeme Russ #define MSR_AMD64_IBSCTL 0xc001103a 23498568f0fSGraeme Russ #define MSR_AMD64_IBSBRTARGET 0xc001103b 235dc68584bSSimon Glass #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 236dc68584bSSimon Glass 237dc68584bSSimon Glass /* Fam 16h MSRs */ 238dc68584bSSimon Glass #define MSR_F16H_L2I_PERF_CTL 0xc0010230 239dc68584bSSimon Glass #define MSR_F16H_L2I_PERF_CTR 0xc0010231 24098568f0fSGraeme Russ 24198568f0fSGraeme Russ /* Fam 15h MSRs */ 24298568f0fSGraeme Russ #define MSR_F15H_PERF_CTL 0xc0010200 24398568f0fSGraeme Russ #define MSR_F15H_PERF_CTR 0xc0010201 244dc68584bSSimon Glass #define MSR_F15H_NB_PERF_CTL 0xc0010240 245dc68584bSSimon Glass #define MSR_F15H_NB_PERF_CTR 0xc0010241 24698568f0fSGraeme Russ 24798568f0fSGraeme Russ /* Fam 10h MSRs */ 24898568f0fSGraeme Russ #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 24998568f0fSGraeme Russ #define FAM10H_MMIO_CONF_ENABLE (1<<0) 25098568f0fSGraeme Russ #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 25198568f0fSGraeme Russ #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 25298568f0fSGraeme Russ #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 25398568f0fSGraeme Russ #define FAM10H_MMIO_CONF_BASE_SHIFT 20 25498568f0fSGraeme Russ #define MSR_FAM10H_NODE_ID 0xc001100c 25598568f0fSGraeme Russ 25698568f0fSGraeme Russ /* K8 MSRs */ 25798568f0fSGraeme Russ #define MSR_K8_TOP_MEM1 0xc001001a 25898568f0fSGraeme Russ #define MSR_K8_TOP_MEM2 0xc001001d 25998568f0fSGraeme Russ #define MSR_K8_SYSCFG 0xc0010010 26098568f0fSGraeme Russ #define MSR_K8_INT_PENDING_MSG 0xc0010055 26198568f0fSGraeme Russ /* C1E active bits in int pending message */ 26298568f0fSGraeme Russ #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 26398568f0fSGraeme Russ #define MSR_K8_TSEG_ADDR 0xc0010112 26498568f0fSGraeme Russ #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 26598568f0fSGraeme Russ #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 26698568f0fSGraeme Russ #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 26798568f0fSGraeme Russ 26898568f0fSGraeme Russ /* K7 MSRs */ 26998568f0fSGraeme Russ #define MSR_K7_EVNTSEL0 0xc0010000 27098568f0fSGraeme Russ #define MSR_K7_PERFCTR0 0xc0010004 27198568f0fSGraeme Russ #define MSR_K7_EVNTSEL1 0xc0010001 27298568f0fSGraeme Russ #define MSR_K7_PERFCTR1 0xc0010005 27398568f0fSGraeme Russ #define MSR_K7_EVNTSEL2 0xc0010002 27498568f0fSGraeme Russ #define MSR_K7_PERFCTR2 0xc0010006 27598568f0fSGraeme Russ #define MSR_K7_EVNTSEL3 0xc0010003 27698568f0fSGraeme Russ #define MSR_K7_PERFCTR3 0xc0010007 27798568f0fSGraeme Russ #define MSR_K7_CLK_CTL 0xc001001b 27898568f0fSGraeme Russ #define MSR_K7_HWCR 0xc0010015 27998568f0fSGraeme Russ #define MSR_K7_FID_VID_CTL 0xc0010041 28098568f0fSGraeme Russ #define MSR_K7_FID_VID_STATUS 0xc0010042 28198568f0fSGraeme Russ 28298568f0fSGraeme Russ /* K6 MSRs */ 28398568f0fSGraeme Russ #define MSR_K6_WHCR 0xc0000082 28498568f0fSGraeme Russ #define MSR_K6_UWCCR 0xc0000085 28598568f0fSGraeme Russ #define MSR_K6_EPMR 0xc0000086 28698568f0fSGraeme Russ #define MSR_K6_PSOR 0xc0000087 28798568f0fSGraeme Russ #define MSR_K6_PFIR 0xc0000088 28898568f0fSGraeme Russ 28998568f0fSGraeme Russ /* Centaur-Hauls/IDT defined MSRs. */ 29098568f0fSGraeme Russ #define MSR_IDT_FCR1 0x00000107 29198568f0fSGraeme Russ #define MSR_IDT_FCR2 0x00000108 29298568f0fSGraeme Russ #define MSR_IDT_FCR3 0x00000109 29398568f0fSGraeme Russ #define MSR_IDT_FCR4 0x0000010a 29498568f0fSGraeme Russ 29598568f0fSGraeme Russ #define MSR_IDT_MCR0 0x00000110 29698568f0fSGraeme Russ #define MSR_IDT_MCR1 0x00000111 29798568f0fSGraeme Russ #define MSR_IDT_MCR2 0x00000112 29898568f0fSGraeme Russ #define MSR_IDT_MCR3 0x00000113 29998568f0fSGraeme Russ #define MSR_IDT_MCR4 0x00000114 30098568f0fSGraeme Russ #define MSR_IDT_MCR5 0x00000115 30198568f0fSGraeme Russ #define MSR_IDT_MCR6 0x00000116 30298568f0fSGraeme Russ #define MSR_IDT_MCR7 0x00000117 30398568f0fSGraeme Russ #define MSR_IDT_MCR_CTRL 0x00000120 30498568f0fSGraeme Russ 30598568f0fSGraeme Russ /* VIA Cyrix defined MSRs*/ 30698568f0fSGraeme Russ #define MSR_VIA_FCR 0x00001107 30798568f0fSGraeme Russ #define MSR_VIA_LONGHAUL 0x0000110a 30898568f0fSGraeme Russ #define MSR_VIA_RNG 0x0000110b 30998568f0fSGraeme Russ #define MSR_VIA_BCR2 0x00001147 31098568f0fSGraeme Russ 31198568f0fSGraeme Russ /* Transmeta defined MSRs */ 31298568f0fSGraeme Russ #define MSR_TMTA_LONGRUN_CTRL 0x80868010 31398568f0fSGraeme Russ #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 31498568f0fSGraeme Russ #define MSR_TMTA_LRTI_READOUT 0x80868018 31598568f0fSGraeme Russ #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 31698568f0fSGraeme Russ 31798568f0fSGraeme Russ /* Intel defined MSRs. */ 31898568f0fSGraeme Russ #define MSR_IA32_P5_MC_ADDR 0x00000000 31998568f0fSGraeme Russ #define MSR_IA32_P5_MC_TYPE 0x00000001 32098568f0fSGraeme Russ #define MSR_IA32_TSC 0x00000010 32198568f0fSGraeme Russ #define MSR_IA32_PLATFORM_ID 0x00000017 32298568f0fSGraeme Russ #define MSR_IA32_EBL_CR_POWERON 0x0000002a 32398568f0fSGraeme Russ #define MSR_EBC_FREQUENCY_ID 0x0000002c 324dc68584bSSimon Glass #define MSR_SMI_COUNT 0x00000034 32598568f0fSGraeme Russ #define MSR_IA32_FEATURE_CONTROL 0x0000003a 326dc68584bSSimon Glass #define MSR_IA32_TSC_ADJUST 0x0000003b 32798568f0fSGraeme Russ 32898568f0fSGraeme Russ #define FEATURE_CONTROL_LOCKED (1<<0) 32998568f0fSGraeme Russ #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) 33098568f0fSGraeme Russ #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 33198568f0fSGraeme Russ 33298568f0fSGraeme Russ #define MSR_IA32_APICBASE 0x0000001b 33398568f0fSGraeme Russ #define MSR_IA32_APICBASE_BSP (1<<8) 33498568f0fSGraeme Russ #define MSR_IA32_APICBASE_ENABLE (1<<11) 33598568f0fSGraeme Russ #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 33698568f0fSGraeme Russ 337dc68584bSSimon Glass #define MSR_IA32_TSCDEADLINE 0x000006e0 338dc68584bSSimon Glass 33998568f0fSGraeme Russ #define MSR_IA32_UCODE_WRITE 0x00000079 34098568f0fSGraeme Russ #define MSR_IA32_UCODE_REV 0x0000008b 34198568f0fSGraeme Russ 34298568f0fSGraeme Russ #define MSR_IA32_PERF_STATUS 0x00000198 34398568f0fSGraeme Russ #define MSR_IA32_PERF_CTL 0x00000199 344dc68584bSSimon Glass #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 345dc68584bSSimon Glass #define MSR_AMD_PERF_STATUS 0xc0010063 346dc68584bSSimon Glass #define MSR_AMD_PERF_CTL 0xc0010062 34798568f0fSGraeme Russ 348bb80be39SSimon Glass #define MSR_PMG_CST_CONFIG_CTL 0x000000e2 349bb80be39SSimon Glass #define MSR_PMG_IO_CAPTURE_ADR 0x000000e4 35098568f0fSGraeme Russ #define MSR_IA32_MPERF 0x000000e7 35198568f0fSGraeme Russ #define MSR_IA32_APERF 0x000000e8 35298568f0fSGraeme Russ 35398568f0fSGraeme Russ #define MSR_IA32_THERM_CONTROL 0x0000019a 35498568f0fSGraeme Russ #define MSR_IA32_THERM_INTERRUPT 0x0000019b 35598568f0fSGraeme Russ 35698568f0fSGraeme Russ #define THERM_INT_HIGH_ENABLE (1 << 0) 35798568f0fSGraeme Russ #define THERM_INT_LOW_ENABLE (1 << 1) 35898568f0fSGraeme Russ #define THERM_INT_PLN_ENABLE (1 << 24) 35998568f0fSGraeme Russ 36098568f0fSGraeme Russ #define MSR_IA32_THERM_STATUS 0x0000019c 36198568f0fSGraeme Russ 36298568f0fSGraeme Russ #define THERM_STATUS_PROCHOT (1 << 0) 36398568f0fSGraeme Russ #define THERM_STATUS_POWER_LIMIT (1 << 10) 36498568f0fSGraeme Russ 36598568f0fSGraeme Russ #define MSR_THERM2_CTL 0x0000019d 36698568f0fSGraeme Russ 36798568f0fSGraeme Russ #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 36898568f0fSGraeme Russ 36998568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE 0x000001a0 370*ede97093SSimon Glass #define H_MISC_DISABLE_TURBO (1 << 6) 37198568f0fSGraeme Russ 37298568f0fSGraeme Russ #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 37398568f0fSGraeme Russ 37498568f0fSGraeme Russ #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 375dc68584bSSimon Glass #define ENERGY_PERF_BIAS_PERFORMANCE 0 376dc68584bSSimon Glass #define ENERGY_PERF_BIAS_NORMAL 6 377dc68584bSSimon Glass #define ENERGY_PERF_BIAS_POWERSAVE 15 37898568f0fSGraeme Russ 37998568f0fSGraeme Russ #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 38098568f0fSGraeme Russ 38198568f0fSGraeme Russ #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 38298568f0fSGraeme Russ #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 38398568f0fSGraeme Russ 38498568f0fSGraeme Russ #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 38598568f0fSGraeme Russ 38698568f0fSGraeme Russ #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 38798568f0fSGraeme Russ #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 38898568f0fSGraeme Russ #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 38998568f0fSGraeme Russ 39098568f0fSGraeme Russ /* Thermal Thresholds Support */ 39198568f0fSGraeme Russ #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 39298568f0fSGraeme Russ #define THERM_SHIFT_THRESHOLD0 8 39398568f0fSGraeme Russ #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 39498568f0fSGraeme Russ #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 39598568f0fSGraeme Russ #define THERM_SHIFT_THRESHOLD1 16 39698568f0fSGraeme Russ #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 39798568f0fSGraeme Russ #define THERM_STATUS_THRESHOLD0 (1 << 6) 39898568f0fSGraeme Russ #define THERM_LOG_THRESHOLD0 (1 << 7) 39998568f0fSGraeme Russ #define THERM_STATUS_THRESHOLD1 (1 << 8) 40098568f0fSGraeme Russ #define THERM_LOG_THRESHOLD1 (1 << 9) 40198568f0fSGraeme Russ 40298568f0fSGraeme Russ /* MISC_ENABLE bits: architectural */ 40398568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0) 40498568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1) 40598568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_EMON (1ULL << 7) 40698568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11) 40798568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12) 40898568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16) 40998568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) 41098568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << 22) 41198568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << 23) 41298568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34) 41398568f0fSGraeme Russ 41498568f0fSGraeme Russ /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 41598568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << 2) 41698568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << 3) 41798568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4) 41898568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << 6) 41998568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << 8) 42098568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << 9) 42198568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_FERR (1ULL << 10) 42298568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << 10) 42398568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << 13) 42498568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << 19) 42598568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << 20) 42698568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << 24) 42798568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << 37) 42898568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38) 42998568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39) 43098568f0fSGraeme Russ 431dc68584bSSimon Glass #define MSR_IA32_TSC_DEADLINE 0x000006E0 432dc68584bSSimon Glass 43398568f0fSGraeme Russ /* P4/Xeon+ specific */ 43498568f0fSGraeme Russ #define MSR_IA32_MCG_EAX 0x00000180 43598568f0fSGraeme Russ #define MSR_IA32_MCG_EBX 0x00000181 43698568f0fSGraeme Russ #define MSR_IA32_MCG_ECX 0x00000182 43798568f0fSGraeme Russ #define MSR_IA32_MCG_EDX 0x00000183 43898568f0fSGraeme Russ #define MSR_IA32_MCG_ESI 0x00000184 43998568f0fSGraeme Russ #define MSR_IA32_MCG_EDI 0x00000185 44098568f0fSGraeme Russ #define MSR_IA32_MCG_EBP 0x00000186 44198568f0fSGraeme Russ #define MSR_IA32_MCG_ESP 0x00000187 44298568f0fSGraeme Russ #define MSR_IA32_MCG_EFLAGS 0x00000188 44398568f0fSGraeme Russ #define MSR_IA32_MCG_EIP 0x00000189 44498568f0fSGraeme Russ #define MSR_IA32_MCG_RESERVED 0x0000018a 44598568f0fSGraeme Russ 44698568f0fSGraeme Russ /* Pentium IV performance counter MSRs */ 44798568f0fSGraeme Russ #define MSR_P4_BPU_PERFCTR0 0x00000300 44898568f0fSGraeme Russ #define MSR_P4_BPU_PERFCTR1 0x00000301 44998568f0fSGraeme Russ #define MSR_P4_BPU_PERFCTR2 0x00000302 45098568f0fSGraeme Russ #define MSR_P4_BPU_PERFCTR3 0x00000303 45198568f0fSGraeme Russ #define MSR_P4_MS_PERFCTR0 0x00000304 45298568f0fSGraeme Russ #define MSR_P4_MS_PERFCTR1 0x00000305 45398568f0fSGraeme Russ #define MSR_P4_MS_PERFCTR2 0x00000306 45498568f0fSGraeme Russ #define MSR_P4_MS_PERFCTR3 0x00000307 45598568f0fSGraeme Russ #define MSR_P4_FLAME_PERFCTR0 0x00000308 45698568f0fSGraeme Russ #define MSR_P4_FLAME_PERFCTR1 0x00000309 45798568f0fSGraeme Russ #define MSR_P4_FLAME_PERFCTR2 0x0000030a 45898568f0fSGraeme Russ #define MSR_P4_FLAME_PERFCTR3 0x0000030b 45998568f0fSGraeme Russ #define MSR_P4_IQ_PERFCTR0 0x0000030c 46098568f0fSGraeme Russ #define MSR_P4_IQ_PERFCTR1 0x0000030d 46198568f0fSGraeme Russ #define MSR_P4_IQ_PERFCTR2 0x0000030e 46298568f0fSGraeme Russ #define MSR_P4_IQ_PERFCTR3 0x0000030f 46398568f0fSGraeme Russ #define MSR_P4_IQ_PERFCTR4 0x00000310 46498568f0fSGraeme Russ #define MSR_P4_IQ_PERFCTR5 0x00000311 46598568f0fSGraeme Russ #define MSR_P4_BPU_CCCR0 0x00000360 46698568f0fSGraeme Russ #define MSR_P4_BPU_CCCR1 0x00000361 46798568f0fSGraeme Russ #define MSR_P4_BPU_CCCR2 0x00000362 46898568f0fSGraeme Russ #define MSR_P4_BPU_CCCR3 0x00000363 46998568f0fSGraeme Russ #define MSR_P4_MS_CCCR0 0x00000364 47098568f0fSGraeme Russ #define MSR_P4_MS_CCCR1 0x00000365 47198568f0fSGraeme Russ #define MSR_P4_MS_CCCR2 0x00000366 47298568f0fSGraeme Russ #define MSR_P4_MS_CCCR3 0x00000367 47398568f0fSGraeme Russ #define MSR_P4_FLAME_CCCR0 0x00000368 47498568f0fSGraeme Russ #define MSR_P4_FLAME_CCCR1 0x00000369 47598568f0fSGraeme Russ #define MSR_P4_FLAME_CCCR2 0x0000036a 47698568f0fSGraeme Russ #define MSR_P4_FLAME_CCCR3 0x0000036b 47798568f0fSGraeme Russ #define MSR_P4_IQ_CCCR0 0x0000036c 47898568f0fSGraeme Russ #define MSR_P4_IQ_CCCR1 0x0000036d 47998568f0fSGraeme Russ #define MSR_P4_IQ_CCCR2 0x0000036e 48098568f0fSGraeme Russ #define MSR_P4_IQ_CCCR3 0x0000036f 48198568f0fSGraeme Russ #define MSR_P4_IQ_CCCR4 0x00000370 48298568f0fSGraeme Russ #define MSR_P4_IQ_CCCR5 0x00000371 48398568f0fSGraeme Russ #define MSR_P4_ALF_ESCR0 0x000003ca 48498568f0fSGraeme Russ #define MSR_P4_ALF_ESCR1 0x000003cb 48598568f0fSGraeme Russ #define MSR_P4_BPU_ESCR0 0x000003b2 48698568f0fSGraeme Russ #define MSR_P4_BPU_ESCR1 0x000003b3 48798568f0fSGraeme Russ #define MSR_P4_BSU_ESCR0 0x000003a0 48898568f0fSGraeme Russ #define MSR_P4_BSU_ESCR1 0x000003a1 48998568f0fSGraeme Russ #define MSR_P4_CRU_ESCR0 0x000003b8 49098568f0fSGraeme Russ #define MSR_P4_CRU_ESCR1 0x000003b9 49198568f0fSGraeme Russ #define MSR_P4_CRU_ESCR2 0x000003cc 49298568f0fSGraeme Russ #define MSR_P4_CRU_ESCR3 0x000003cd 49398568f0fSGraeme Russ #define MSR_P4_CRU_ESCR4 0x000003e0 49498568f0fSGraeme Russ #define MSR_P4_CRU_ESCR5 0x000003e1 49598568f0fSGraeme Russ #define MSR_P4_DAC_ESCR0 0x000003a8 49698568f0fSGraeme Russ #define MSR_P4_DAC_ESCR1 0x000003a9 49798568f0fSGraeme Russ #define MSR_P4_FIRM_ESCR0 0x000003a4 49898568f0fSGraeme Russ #define MSR_P4_FIRM_ESCR1 0x000003a5 49998568f0fSGraeme Russ #define MSR_P4_FLAME_ESCR0 0x000003a6 50098568f0fSGraeme Russ #define MSR_P4_FLAME_ESCR1 0x000003a7 50198568f0fSGraeme Russ #define MSR_P4_FSB_ESCR0 0x000003a2 50298568f0fSGraeme Russ #define MSR_P4_FSB_ESCR1 0x000003a3 50398568f0fSGraeme Russ #define MSR_P4_IQ_ESCR0 0x000003ba 50498568f0fSGraeme Russ #define MSR_P4_IQ_ESCR1 0x000003bb 50598568f0fSGraeme Russ #define MSR_P4_IS_ESCR0 0x000003b4 50698568f0fSGraeme Russ #define MSR_P4_IS_ESCR1 0x000003b5 50798568f0fSGraeme Russ #define MSR_P4_ITLB_ESCR0 0x000003b6 50898568f0fSGraeme Russ #define MSR_P4_ITLB_ESCR1 0x000003b7 50998568f0fSGraeme Russ #define MSR_P4_IX_ESCR0 0x000003c8 51098568f0fSGraeme Russ #define MSR_P4_IX_ESCR1 0x000003c9 51198568f0fSGraeme Russ #define MSR_P4_MOB_ESCR0 0x000003aa 51298568f0fSGraeme Russ #define MSR_P4_MOB_ESCR1 0x000003ab 51398568f0fSGraeme Russ #define MSR_P4_MS_ESCR0 0x000003c0 51498568f0fSGraeme Russ #define MSR_P4_MS_ESCR1 0x000003c1 51598568f0fSGraeme Russ #define MSR_P4_PMH_ESCR0 0x000003ac 51698568f0fSGraeme Russ #define MSR_P4_PMH_ESCR1 0x000003ad 51798568f0fSGraeme Russ #define MSR_P4_RAT_ESCR0 0x000003bc 51898568f0fSGraeme Russ #define MSR_P4_RAT_ESCR1 0x000003bd 51998568f0fSGraeme Russ #define MSR_P4_SAAT_ESCR0 0x000003ae 52098568f0fSGraeme Russ #define MSR_P4_SAAT_ESCR1 0x000003af 52198568f0fSGraeme Russ #define MSR_P4_SSU_ESCR0 0x000003be 52298568f0fSGraeme Russ #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 52398568f0fSGraeme Russ 52498568f0fSGraeme Russ #define MSR_P4_TBPU_ESCR0 0x000003c2 52598568f0fSGraeme Russ #define MSR_P4_TBPU_ESCR1 0x000003c3 52698568f0fSGraeme Russ #define MSR_P4_TC_ESCR0 0x000003c4 52798568f0fSGraeme Russ #define MSR_P4_TC_ESCR1 0x000003c5 52898568f0fSGraeme Russ #define MSR_P4_U2L_ESCR0 0x000003b0 52998568f0fSGraeme Russ #define MSR_P4_U2L_ESCR1 0x000003b1 53098568f0fSGraeme Russ 53198568f0fSGraeme Russ #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 53298568f0fSGraeme Russ 53398568f0fSGraeme Russ /* Intel Core-based CPU performance counters */ 53498568f0fSGraeme Russ #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 53598568f0fSGraeme Russ #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 53698568f0fSGraeme Russ #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 53798568f0fSGraeme Russ #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 53898568f0fSGraeme Russ #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 53998568f0fSGraeme Russ #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 54098568f0fSGraeme Russ #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 54198568f0fSGraeme Russ 54298568f0fSGraeme Russ /* Geode defined MSRs */ 54398568f0fSGraeme Russ #define MSR_GEODE_BUSCONT_CONF0 0x00001900 54498568f0fSGraeme Russ 54598568f0fSGraeme Russ /* Intel VT MSRs */ 54698568f0fSGraeme Russ #define MSR_IA32_VMX_BASIC 0x00000480 54798568f0fSGraeme Russ #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 54898568f0fSGraeme Russ #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 54998568f0fSGraeme Russ #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 55098568f0fSGraeme Russ #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 55198568f0fSGraeme Russ #define MSR_IA32_VMX_MISC 0x00000485 55298568f0fSGraeme Russ #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 55398568f0fSGraeme Russ #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 55498568f0fSGraeme Russ #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 55598568f0fSGraeme Russ #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 55698568f0fSGraeme Russ #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 55798568f0fSGraeme Russ #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 55898568f0fSGraeme Russ #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 559dc68584bSSimon Glass #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 560dc68584bSSimon Glass #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 561dc68584bSSimon Glass #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 562dc68584bSSimon Glass #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 563dc68584bSSimon Glass #define MSR_IA32_VMX_VMFUNC 0x00000491 56498568f0fSGraeme Russ 565dc68584bSSimon Glass /* VMX_BASIC bits and bitmasks */ 566dc68584bSSimon Glass #define VMX_BASIC_VMCS_SIZE_SHIFT 32 567dc68584bSSimon Glass #define VMX_BASIC_64 0x0001000000000000LLU 568dc68584bSSimon Glass #define VMX_BASIC_MEM_TYPE_SHIFT 50 569dc68584bSSimon Glass #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 570dc68584bSSimon Glass #define VMX_BASIC_MEM_TYPE_WB 6LLU 571dc68584bSSimon Glass #define VMX_BASIC_INOUT 0x0040000000000000LLU 572dc68584bSSimon Glass 573dc68584bSSimon Glass /* MSR_IA32_VMX_MISC bits */ 574dc68584bSSimon Glass #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 575dc68584bSSimon Glass #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 57698568f0fSGraeme Russ /* AMD-V MSRs */ 57798568f0fSGraeme Russ 57898568f0fSGraeme Russ #define MSR_VM_CR 0xc0010114 57998568f0fSGraeme Russ #define MSR_VM_IGNNE 0xc0010115 58098568f0fSGraeme Russ #define MSR_VM_HSAVE_PA 0xc0010117 58198568f0fSGraeme Russ 58298568f0fSGraeme Russ #endif /* _ASM_X86_MSR_INDEX_H */ 583