1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 298568f0fSGraeme Russ /* 398568f0fSGraeme Russ * Taken from the linux kernel file of the same name 498568f0fSGraeme Russ * 598568f0fSGraeme Russ * (C) Copyright 2012 698568f0fSGraeme Russ * Graeme Russ, <graeme.russ@gmail.com> 798568f0fSGraeme Russ */ 898568f0fSGraeme Russ 998568f0fSGraeme Russ #ifndef _ASM_X86_MSR_INDEX_H 1098568f0fSGraeme Russ #define _ASM_X86_MSR_INDEX_H 1198568f0fSGraeme Russ 1298568f0fSGraeme Russ /* CPU model specific register (MSR) numbers */ 1398568f0fSGraeme Russ 1498568f0fSGraeme Russ /* x86-64 specific MSRs */ 1598568f0fSGraeme Russ #define MSR_EFER 0xc0000080 /* extended feature register */ 1698568f0fSGraeme Russ #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 1798568f0fSGraeme Russ #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 1898568f0fSGraeme Russ #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 1998568f0fSGraeme Russ #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 2098568f0fSGraeme Russ #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 2198568f0fSGraeme Russ #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 2298568f0fSGraeme Russ #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 2398568f0fSGraeme Russ #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 2498568f0fSGraeme Russ 2598568f0fSGraeme Russ /* EFER bits: */ 2698568f0fSGraeme Russ #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 2798568f0fSGraeme Russ #define _EFER_LME 8 /* Long mode enable */ 2898568f0fSGraeme Russ #define _EFER_LMA 10 /* Long mode active (read-only) */ 2998568f0fSGraeme Russ #define _EFER_NX 11 /* No execute enable */ 3098568f0fSGraeme Russ #define _EFER_SVME 12 /* Enable virtualization */ 3198568f0fSGraeme Russ #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 3298568f0fSGraeme Russ #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 3398568f0fSGraeme Russ 3498568f0fSGraeme Russ #define EFER_SCE (1<<_EFER_SCE) 3598568f0fSGraeme Russ #define EFER_LME (1<<_EFER_LME) 3698568f0fSGraeme Russ #define EFER_LMA (1<<_EFER_LMA) 3798568f0fSGraeme Russ #define EFER_NX (1<<_EFER_NX) 3898568f0fSGraeme Russ #define EFER_SVME (1<<_EFER_SVME) 3998568f0fSGraeme Russ #define EFER_LMSLE (1<<_EFER_LMSLE) 4098568f0fSGraeme Russ #define EFER_FFXSR (1<<_EFER_FFXSR) 4198568f0fSGraeme Russ 4298568f0fSGraeme Russ /* Intel MSRs. Some also available on other CPUs */ 438bf08b42SSimon Glass #define MSR_PIC_MSG_CONTROL 0x2e 448bf08b42SSimon Glass #define PLATFORM_INFO_SET_TDP (1 << 29) 458bf08b42SSimon Glass 4698568f0fSGraeme Russ #define MSR_IA32_PERFCTR0 0x000000c1 4798568f0fSGraeme Russ #define MSR_IA32_PERFCTR1 0x000000c2 4898568f0fSGraeme Russ #define MSR_FSB_FREQ 0x000000cd 49dc68584bSSimon Glass #define MSR_NHM_PLATFORM_INFO 0x000000ce 5098568f0fSGraeme Russ 5198568f0fSGraeme Russ #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 5298568f0fSGraeme Russ #define NHM_C3_AUTO_DEMOTE (1UL << 25) 5398568f0fSGraeme Russ #define NHM_C1_AUTO_DEMOTE (1UL << 26) 5498568f0fSGraeme Russ #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 55dc68584bSSimon Glass #define SNB_C1_AUTO_UNDEMOTE (1UL << 27) 56dc68584bSSimon Glass #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) 5798568f0fSGraeme Russ 58ede97093SSimon Glass #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0x000000cd 59dc68584bSSimon Glass #define MSR_PLATFORM_INFO 0x000000ce 60ede97093SSimon Glass #define MSR_PMG_CST_CONFIG_CONTROL 0x000000e2 61ede97093SSimon Glass #define SINGLE_PCTL (1 << 11) 62ede97093SSimon Glass 6398568f0fSGraeme Russ #define MSR_MTRRcap 0x000000fe 6498568f0fSGraeme Russ #define MSR_IA32_BBL_CR_CTL 0x00000119 6598568f0fSGraeme Russ #define MSR_IA32_BBL_CR_CTL3 0x0000011e 66ede97093SSimon Glass #define MSR_POWER_MISC 0x00000120 67ede97093SSimon Glass #define ENABLE_ULFM_AUTOCM_MASK (1 << 2) 68ede97093SSimon Glass #define ENABLE_INDP_AUTOCM_MASK (1 << 3) 6998568f0fSGraeme Russ 7098568f0fSGraeme Russ #define MSR_IA32_SYSENTER_CS 0x00000174 7198568f0fSGraeme Russ #define MSR_IA32_SYSENTER_ESP 0x00000175 7298568f0fSGraeme Russ #define MSR_IA32_SYSENTER_EIP 0x00000176 7398568f0fSGraeme Russ 7498568f0fSGraeme Russ #define MSR_IA32_MCG_CAP 0x00000179 7598568f0fSGraeme Russ #define MSR_IA32_MCG_STATUS 0x0000017a 7698568f0fSGraeme Russ #define MSR_IA32_MCG_CTL 0x0000017b 7798568f0fSGraeme Russ 788bf08b42SSimon Glass #define MSR_FLEX_RATIO 0x194 798bf08b42SSimon Glass #define FLEX_RATIO_LOCK (1 << 20) 808bf08b42SSimon Glass #define FLEX_RATIO_EN (1 << 16) 818bf08b42SSimon Glass 82ede97093SSimon Glass #define MSR_IA32_MISC_ENABLES 0x000001a0 838bf08b42SSimon Glass #define MSR_TEMPERATURE_TARGET 0x1a2 8498568f0fSGraeme Russ #define MSR_OFFCORE_RSP_0 0x000001a6 8598568f0fSGraeme Russ #define MSR_OFFCORE_RSP_1 0x000001a7 868bf08b42SSimon Glass #define MSR_MISC_PWR_MGMT 0x1aa 878bf08b42SSimon Glass #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) 88dc68584bSSimon Glass #define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad 89dc68584bSSimon Glass #define MSR_IVT_TURBO_RATIO_LIMIT 0x000001ae 90dc68584bSSimon Glass 918bf08b42SSimon Glass #define MSR_IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 928bf08b42SSimon Glass #define ENERGY_POLICY_PERFORMANCE 0 938bf08b42SSimon Glass #define ENERGY_POLICY_NORMAL 6 948bf08b42SSimon Glass #define ENERGY_POLICY_POWERSAVE 15 958bf08b42SSimon Glass 96dc68584bSSimon Glass #define MSR_LBR_SELECT 0x000001c8 97dc68584bSSimon Glass #define MSR_LBR_TOS 0x000001c9 988bf08b42SSimon Glass #define MSR_IA32_PLATFORM_DCA_CAP 0x1f8 99ede97093SSimon Glass #define MSR_POWER_CTL 0x000001fc 100dc68584bSSimon Glass #define MSR_LBR_NHM_FROM 0x00000680 101dc68584bSSimon Glass #define MSR_LBR_NHM_TO 0x000006c0 102dc68584bSSimon Glass #define MSR_LBR_CORE_FROM 0x00000040 103dc68584bSSimon Glass #define MSR_LBR_CORE_TO 0x00000060 10498568f0fSGraeme Russ 10598568f0fSGraeme Russ #define MSR_IA32_PEBS_ENABLE 0x000003f1 10698568f0fSGraeme Russ #define MSR_IA32_DS_AREA 0x00000600 10798568f0fSGraeme Russ #define MSR_IA32_PERF_CAPABILITIES 0x00000345 108dc68584bSSimon Glass #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 10998568f0fSGraeme Russ 11098568f0fSGraeme Russ #define MSR_MTRRfix64K_00000 0x00000250 11198568f0fSGraeme Russ #define MSR_MTRRfix16K_80000 0x00000258 11298568f0fSGraeme Russ #define MSR_MTRRfix16K_A0000 0x00000259 11398568f0fSGraeme Russ #define MSR_MTRRfix4K_C0000 0x00000268 11498568f0fSGraeme Russ #define MSR_MTRRfix4K_C8000 0x00000269 11598568f0fSGraeme Russ #define MSR_MTRRfix4K_D0000 0x0000026a 11698568f0fSGraeme Russ #define MSR_MTRRfix4K_D8000 0x0000026b 11798568f0fSGraeme Russ #define MSR_MTRRfix4K_E0000 0x0000026c 11898568f0fSGraeme Russ #define MSR_MTRRfix4K_E8000 0x0000026d 11998568f0fSGraeme Russ #define MSR_MTRRfix4K_F0000 0x0000026e 12098568f0fSGraeme Russ #define MSR_MTRRfix4K_F8000 0x0000026f 12198568f0fSGraeme Russ #define MSR_MTRRdefType 0x000002ff 12298568f0fSGraeme Russ 12398568f0fSGraeme Russ #define MSR_IA32_CR_PAT 0x00000277 12498568f0fSGraeme Russ 12598568f0fSGraeme Russ #define MSR_IA32_DEBUGCTLMSR 0x000001d9 12698568f0fSGraeme Russ #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 12798568f0fSGraeme Russ #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 12898568f0fSGraeme Russ #define MSR_IA32_LASTINTFROMIP 0x000001dd 12998568f0fSGraeme Russ #define MSR_IA32_LASTINTTOIP 0x000001de 13098568f0fSGraeme Russ 13198568f0fSGraeme Russ /* DEBUGCTLMSR bits (others vary by model): */ 132dc68584bSSimon Glass #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 133dc68584bSSimon Glass /* single-step on branches */ 13498568f0fSGraeme Russ #define DEBUGCTLMSR_BTF (1UL << 1) 13598568f0fSGraeme Russ #define DEBUGCTLMSR_TR (1UL << 6) 13698568f0fSGraeme Russ #define DEBUGCTLMSR_BTS (1UL << 7) 13798568f0fSGraeme Russ #define DEBUGCTLMSR_BTINT (1UL << 8) 13898568f0fSGraeme Russ #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 13998568f0fSGraeme Russ #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 14098568f0fSGraeme Russ #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 14198568f0fSGraeme Russ 142dc68584bSSimon Glass #define MSR_IA32_POWER_CTL 0x000001fc 143dc68584bSSimon Glass 14498568f0fSGraeme Russ #define MSR_IA32_MC0_CTL 0x00000400 14598568f0fSGraeme Russ #define MSR_IA32_MC0_STATUS 0x00000401 14698568f0fSGraeme Russ #define MSR_IA32_MC0_ADDR 0x00000402 14798568f0fSGraeme Russ #define MSR_IA32_MC0_MISC 0x00000403 14898568f0fSGraeme Russ 149dc68584bSSimon Glass /* C-state Residency Counters */ 150dc68584bSSimon Glass #define MSR_PKG_C3_RESIDENCY 0x000003f8 151dc68584bSSimon Glass #define MSR_PKG_C6_RESIDENCY 0x000003f9 152dc68584bSSimon Glass #define MSR_PKG_C7_RESIDENCY 0x000003fa 153dc68584bSSimon Glass #define MSR_CORE_C3_RESIDENCY 0x000003fc 154dc68584bSSimon Glass #define MSR_CORE_C6_RESIDENCY 0x000003fd 155dc68584bSSimon Glass #define MSR_CORE_C7_RESIDENCY 0x000003fe 156dc68584bSSimon Glass #define MSR_PKG_C2_RESIDENCY 0x0000060d 157dc68584bSSimon Glass #define MSR_PKG_C8_RESIDENCY 0x00000630 158dc68584bSSimon Glass #define MSR_PKG_C9_RESIDENCY 0x00000631 159dc68584bSSimon Glass #define MSR_PKG_C10_RESIDENCY 0x00000632 160dc68584bSSimon Glass 161dc68584bSSimon Glass /* Run Time Average Power Limiting (RAPL) Interface */ 162dc68584bSSimon Glass 163ede97093SSimon Glass #define MSR_PKG_POWER_SKU_UNIT 0x00000606 164dc68584bSSimon Glass 1658bf08b42SSimon Glass #define MSR_C_STATE_LATENCY_CONTROL_0 0x60a 1668bf08b42SSimon Glass #define MSR_C_STATE_LATENCY_CONTROL_1 0x60b 1678bf08b42SSimon Glass #define MSR_C_STATE_LATENCY_CONTROL_2 0x60c 1688bf08b42SSimon Glass #define MSR_C_STATE_LATENCY_CONTROL_3 0x633 1698bf08b42SSimon Glass #define MSR_C_STATE_LATENCY_CONTROL_4 0x634 1708bf08b42SSimon Glass #define MSR_C_STATE_LATENCY_CONTROL_5 0x635 1718bf08b42SSimon Glass #define IRTL_VALID (1 << 15) 1728bf08b42SSimon Glass #define IRTL_1_NS (0 << 10) 1738bf08b42SSimon Glass #define IRTL_32_NS (1 << 10) 1748bf08b42SSimon Glass #define IRTL_1024_NS (2 << 10) 1758bf08b42SSimon Glass #define IRTL_32768_NS (3 << 10) 1768bf08b42SSimon Glass #define IRTL_1048576_NS (4 << 10) 1778bf08b42SSimon Glass #define IRTL_33554432_NS (5 << 10) 1788bf08b42SSimon Glass #define IRTL_RESPONSE_MASK (0x3ff) 1798bf08b42SSimon Glass 180dc68584bSSimon Glass #define MSR_PKG_POWER_LIMIT 0x00000610 1818bf08b42SSimon Glass /* long duration in low dword, short duration in high dword */ 1828bf08b42SSimon Glass #define PKG_POWER_LIMIT_MASK 0x7fff 1838bf08b42SSimon Glass #define PKG_POWER_LIMIT_EN (1 << 15) 1848bf08b42SSimon Glass #define PKG_POWER_LIMIT_CLAMP (1 << 16) 1858bf08b42SSimon Glass #define PKG_POWER_LIMIT_TIME_SHIFT 17 1868bf08b42SSimon Glass #define PKG_POWER_LIMIT_TIME_MASK 0x7f 1878bf08b42SSimon Glass 188dc68584bSSimon Glass #define MSR_PKG_ENERGY_STATUS 0x00000611 189dc68584bSSimon Glass #define MSR_PKG_PERF_STATUS 0x00000613 190dc68584bSSimon Glass #define MSR_PKG_POWER_INFO 0x00000614 191dc68584bSSimon Glass 192dc68584bSSimon Glass #define MSR_DRAM_POWER_LIMIT 0x00000618 193dc68584bSSimon Glass #define MSR_DRAM_ENERGY_STATUS 0x00000619 194dc68584bSSimon Glass #define MSR_DRAM_PERF_STATUS 0x0000061b 195dc68584bSSimon Glass #define MSR_DRAM_POWER_INFO 0x0000061c 196dc68584bSSimon Glass 197dc68584bSSimon Glass #define MSR_PP0_POWER_LIMIT 0x00000638 198dc68584bSSimon Glass #define MSR_PP0_ENERGY_STATUS 0x00000639 199dc68584bSSimon Glass #define MSR_PP0_POLICY 0x0000063a 200dc68584bSSimon Glass #define MSR_PP0_PERF_STATUS 0x0000063b 201dc68584bSSimon Glass 202dc68584bSSimon Glass #define MSR_PP1_POWER_LIMIT 0x00000640 203dc68584bSSimon Glass #define MSR_PP1_ENERGY_STATUS 0x00000641 204dc68584bSSimon Glass #define MSR_PP1_POLICY 0x00000642 2058bf08b42SSimon Glass #define MSR_CONFIG_TDP_NOMINAL 0x00000648 2068bf08b42SSimon Glass #define MSR_TURBO_ACTIVATION_RATIO 0x0000064c 207dc68584bSSimon Glass #define MSR_CORE_C1_RES 0x00000660 208ede97093SSimon Glass #define MSR_IACORE_RATIOS 0x0000066a 209ede97093SSimon Glass #define MSR_IACORE_TURBO_RATIOS 0x0000066c 210ede97093SSimon Glass #define MSR_IACORE_VIDS 0x0000066b 211ede97093SSimon Glass #define MSR_IACORE_TURBO_VIDS 0x0000066d 212ede97093SSimon Glass #define MSR_PKG_TURBO_CFG1 0x00000670 213ede97093SSimon Glass #define MSR_CPU_TURBO_WKLD_CFG1 0x00000671 214ede97093SSimon Glass #define MSR_CPU_TURBO_WKLD_CFG2 0x00000672 215ede97093SSimon Glass #define MSR_CPU_THERM_CFG1 0x00000673 216ede97093SSimon Glass #define MSR_CPU_THERM_CFG2 0x00000674 217ede97093SSimon Glass #define MSR_CPU_THERM_SENS_CFG 0x00000675 218dc68584bSSimon Glass 21998568f0fSGraeme Russ #define MSR_AMD64_MC0_MASK 0xc0010044 22098568f0fSGraeme Russ 22198568f0fSGraeme Russ #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 22298568f0fSGraeme Russ #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 22398568f0fSGraeme Russ #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 22498568f0fSGraeme Russ #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 22598568f0fSGraeme Russ 22698568f0fSGraeme Russ #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 22798568f0fSGraeme Russ 22898568f0fSGraeme Russ /* These are consecutive and not in the normal 4er MCE bank block */ 22998568f0fSGraeme Russ #define MSR_IA32_MC0_CTL2 0x00000280 23098568f0fSGraeme Russ #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 23198568f0fSGraeme Russ 23298568f0fSGraeme Russ #define MSR_P6_PERFCTR0 0x000000c1 23398568f0fSGraeme Russ #define MSR_P6_PERFCTR1 0x000000c2 23498568f0fSGraeme Russ #define MSR_P6_EVNTSEL0 0x00000186 23598568f0fSGraeme Russ #define MSR_P6_EVNTSEL1 0x00000187 23698568f0fSGraeme Russ 237dc68584bSSimon Glass #define MSR_KNC_PERFCTR0 0x00000020 238dc68584bSSimon Glass #define MSR_KNC_PERFCTR1 0x00000021 239dc68584bSSimon Glass #define MSR_KNC_EVNTSEL0 0x00000028 240dc68584bSSimon Glass #define MSR_KNC_EVNTSEL1 0x00000029 241dc68584bSSimon Glass 242dc68584bSSimon Glass /* Alternative perfctr range with full access. */ 243dc68584bSSimon Glass #define MSR_IA32_PMC0 0x000004c1 244dc68584bSSimon Glass 24598568f0fSGraeme Russ /* AMD64 MSRs. Not complete. See the architecture manual for a more 24698568f0fSGraeme Russ complete list. */ 24798568f0fSGraeme Russ 24898568f0fSGraeme Russ #define MSR_AMD64_PATCH_LEVEL 0x0000008b 249dc68584bSSimon Glass #define MSR_AMD64_TSC_RATIO 0xc0000104 25098568f0fSGraeme Russ #define MSR_AMD64_NB_CFG 0xc001001f 25198568f0fSGraeme Russ #define MSR_AMD64_PATCH_LOADER 0xc0010020 25298568f0fSGraeme Russ #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 25398568f0fSGraeme Russ #define MSR_AMD64_OSVW_STATUS 0xc0010141 254dc68584bSSimon Glass #define MSR_AMD64_LS_CFG 0xc0011020 25598568f0fSGraeme Russ #define MSR_AMD64_DC_CFG 0xc0011022 256dc68584bSSimon Glass #define MSR_AMD64_BU_CFG2 0xc001102a 25798568f0fSGraeme Russ #define MSR_AMD64_IBSFETCHCTL 0xc0011030 25898568f0fSGraeme Russ #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 25998568f0fSGraeme Russ #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 260dc68584bSSimon Glass #define MSR_AMD64_IBSFETCH_REG_COUNT 3 261dc68584bSSimon Glass #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 26298568f0fSGraeme Russ #define MSR_AMD64_IBSOPCTL 0xc0011033 26398568f0fSGraeme Russ #define MSR_AMD64_IBSOPRIP 0xc0011034 26498568f0fSGraeme Russ #define MSR_AMD64_IBSOPDATA 0xc0011035 26598568f0fSGraeme Russ #define MSR_AMD64_IBSOPDATA2 0xc0011036 26698568f0fSGraeme Russ #define MSR_AMD64_IBSOPDATA3 0xc0011037 26798568f0fSGraeme Russ #define MSR_AMD64_IBSDCLINAD 0xc0011038 26898568f0fSGraeme Russ #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 269dc68584bSSimon Glass #define MSR_AMD64_IBSOP_REG_COUNT 7 270dc68584bSSimon Glass #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 27198568f0fSGraeme Russ #define MSR_AMD64_IBSCTL 0xc001103a 27298568f0fSGraeme Russ #define MSR_AMD64_IBSBRTARGET 0xc001103b 273dc68584bSSimon Glass #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 274dc68584bSSimon Glass 275dc68584bSSimon Glass /* Fam 16h MSRs */ 276dc68584bSSimon Glass #define MSR_F16H_L2I_PERF_CTL 0xc0010230 277dc68584bSSimon Glass #define MSR_F16H_L2I_PERF_CTR 0xc0010231 27898568f0fSGraeme Russ 27998568f0fSGraeme Russ /* Fam 15h MSRs */ 28098568f0fSGraeme Russ #define MSR_F15H_PERF_CTL 0xc0010200 28198568f0fSGraeme Russ #define MSR_F15H_PERF_CTR 0xc0010201 282dc68584bSSimon Glass #define MSR_F15H_NB_PERF_CTL 0xc0010240 283dc68584bSSimon Glass #define MSR_F15H_NB_PERF_CTR 0xc0010241 28498568f0fSGraeme Russ 28598568f0fSGraeme Russ /* Fam 10h MSRs */ 28698568f0fSGraeme Russ #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 28798568f0fSGraeme Russ #define FAM10H_MMIO_CONF_ENABLE (1<<0) 28898568f0fSGraeme Russ #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 28998568f0fSGraeme Russ #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 29098568f0fSGraeme Russ #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 29198568f0fSGraeme Russ #define FAM10H_MMIO_CONF_BASE_SHIFT 20 29298568f0fSGraeme Russ #define MSR_FAM10H_NODE_ID 0xc001100c 29398568f0fSGraeme Russ 29498568f0fSGraeme Russ /* K8 MSRs */ 29598568f0fSGraeme Russ #define MSR_K8_TOP_MEM1 0xc001001a 29698568f0fSGraeme Russ #define MSR_K8_TOP_MEM2 0xc001001d 29798568f0fSGraeme Russ #define MSR_K8_SYSCFG 0xc0010010 29898568f0fSGraeme Russ #define MSR_K8_INT_PENDING_MSG 0xc0010055 29998568f0fSGraeme Russ /* C1E active bits in int pending message */ 30098568f0fSGraeme Russ #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 30198568f0fSGraeme Russ #define MSR_K8_TSEG_ADDR 0xc0010112 30298568f0fSGraeme Russ #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 30398568f0fSGraeme Russ #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 30498568f0fSGraeme Russ #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 30598568f0fSGraeme Russ 30698568f0fSGraeme Russ /* K7 MSRs */ 30798568f0fSGraeme Russ #define MSR_K7_EVNTSEL0 0xc0010000 30898568f0fSGraeme Russ #define MSR_K7_PERFCTR0 0xc0010004 30998568f0fSGraeme Russ #define MSR_K7_EVNTSEL1 0xc0010001 31098568f0fSGraeme Russ #define MSR_K7_PERFCTR1 0xc0010005 31198568f0fSGraeme Russ #define MSR_K7_EVNTSEL2 0xc0010002 31298568f0fSGraeme Russ #define MSR_K7_PERFCTR2 0xc0010006 31398568f0fSGraeme Russ #define MSR_K7_EVNTSEL3 0xc0010003 31498568f0fSGraeme Russ #define MSR_K7_PERFCTR3 0xc0010007 31598568f0fSGraeme Russ #define MSR_K7_CLK_CTL 0xc001001b 31698568f0fSGraeme Russ #define MSR_K7_HWCR 0xc0010015 31798568f0fSGraeme Russ #define MSR_K7_FID_VID_CTL 0xc0010041 31898568f0fSGraeme Russ #define MSR_K7_FID_VID_STATUS 0xc0010042 31998568f0fSGraeme Russ 32098568f0fSGraeme Russ /* K6 MSRs */ 32198568f0fSGraeme Russ #define MSR_K6_WHCR 0xc0000082 32298568f0fSGraeme Russ #define MSR_K6_UWCCR 0xc0000085 32398568f0fSGraeme Russ #define MSR_K6_EPMR 0xc0000086 32498568f0fSGraeme Russ #define MSR_K6_PSOR 0xc0000087 32598568f0fSGraeme Russ #define MSR_K6_PFIR 0xc0000088 32698568f0fSGraeme Russ 32798568f0fSGraeme Russ /* Centaur-Hauls/IDT defined MSRs. */ 32898568f0fSGraeme Russ #define MSR_IDT_FCR1 0x00000107 32998568f0fSGraeme Russ #define MSR_IDT_FCR2 0x00000108 33098568f0fSGraeme Russ #define MSR_IDT_FCR3 0x00000109 33198568f0fSGraeme Russ #define MSR_IDT_FCR4 0x0000010a 33298568f0fSGraeme Russ 33398568f0fSGraeme Russ #define MSR_IDT_MCR0 0x00000110 33498568f0fSGraeme Russ #define MSR_IDT_MCR1 0x00000111 33598568f0fSGraeme Russ #define MSR_IDT_MCR2 0x00000112 33698568f0fSGraeme Russ #define MSR_IDT_MCR3 0x00000113 33798568f0fSGraeme Russ #define MSR_IDT_MCR4 0x00000114 33898568f0fSGraeme Russ #define MSR_IDT_MCR5 0x00000115 33998568f0fSGraeme Russ #define MSR_IDT_MCR6 0x00000116 34098568f0fSGraeme Russ #define MSR_IDT_MCR7 0x00000117 34198568f0fSGraeme Russ #define MSR_IDT_MCR_CTRL 0x00000120 34298568f0fSGraeme Russ 34398568f0fSGraeme Russ /* VIA Cyrix defined MSRs*/ 34498568f0fSGraeme Russ #define MSR_VIA_FCR 0x00001107 34598568f0fSGraeme Russ #define MSR_VIA_LONGHAUL 0x0000110a 34698568f0fSGraeme Russ #define MSR_VIA_RNG 0x0000110b 34798568f0fSGraeme Russ #define MSR_VIA_BCR2 0x00001147 34898568f0fSGraeme Russ 34998568f0fSGraeme Russ /* Transmeta defined MSRs */ 35098568f0fSGraeme Russ #define MSR_TMTA_LONGRUN_CTRL 0x80868010 35198568f0fSGraeme Russ #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 35298568f0fSGraeme Russ #define MSR_TMTA_LRTI_READOUT 0x80868018 35398568f0fSGraeme Russ #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 35498568f0fSGraeme Russ 35598568f0fSGraeme Russ /* Intel defined MSRs. */ 35698568f0fSGraeme Russ #define MSR_IA32_P5_MC_ADDR 0x00000000 35798568f0fSGraeme Russ #define MSR_IA32_P5_MC_TYPE 0x00000001 35898568f0fSGraeme Russ #define MSR_IA32_TSC 0x00000010 35998568f0fSGraeme Russ #define MSR_IA32_PLATFORM_ID 0x00000017 36098568f0fSGraeme Russ #define MSR_IA32_EBL_CR_POWERON 0x0000002a 36198568f0fSGraeme Russ #define MSR_EBC_FREQUENCY_ID 0x0000002c 362dc68584bSSimon Glass #define MSR_SMI_COUNT 0x00000034 36398568f0fSGraeme Russ #define MSR_IA32_FEATURE_CONTROL 0x0000003a 364dc68584bSSimon Glass #define MSR_IA32_TSC_ADJUST 0x0000003b 36598568f0fSGraeme Russ 36698568f0fSGraeme Russ #define FEATURE_CONTROL_LOCKED (1<<0) 36798568f0fSGraeme Russ #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) 36898568f0fSGraeme Russ #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 36998568f0fSGraeme Russ 37098568f0fSGraeme Russ #define MSR_IA32_APICBASE 0x0000001b 37198568f0fSGraeme Russ #define MSR_IA32_APICBASE_BSP (1<<8) 37298568f0fSGraeme Russ #define MSR_IA32_APICBASE_ENABLE (1<<11) 37398568f0fSGraeme Russ #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 37498568f0fSGraeme Russ 375dc68584bSSimon Glass #define MSR_IA32_TSCDEADLINE 0x000006e0 376dc68584bSSimon Glass 37798568f0fSGraeme Russ #define MSR_IA32_UCODE_WRITE 0x00000079 37898568f0fSGraeme Russ #define MSR_IA32_UCODE_REV 0x0000008b 37998568f0fSGraeme Russ 38098568f0fSGraeme Russ #define MSR_IA32_PERF_STATUS 0x00000198 38198568f0fSGraeme Russ #define MSR_IA32_PERF_CTL 0x00000199 382dc68584bSSimon Glass #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 383dc68584bSSimon Glass #define MSR_AMD_PERF_STATUS 0xc0010063 384dc68584bSSimon Glass #define MSR_AMD_PERF_CTL 0xc0010062 38598568f0fSGraeme Russ 386bb80be39SSimon Glass #define MSR_PMG_CST_CONFIG_CTL 0x000000e2 387bb80be39SSimon Glass #define MSR_PMG_IO_CAPTURE_ADR 0x000000e4 38898568f0fSGraeme Russ #define MSR_IA32_MPERF 0x000000e7 38998568f0fSGraeme Russ #define MSR_IA32_APERF 0x000000e8 39098568f0fSGraeme Russ 39198568f0fSGraeme Russ #define MSR_IA32_THERM_CONTROL 0x0000019a 39298568f0fSGraeme Russ #define MSR_IA32_THERM_INTERRUPT 0x0000019b 39398568f0fSGraeme Russ 39498568f0fSGraeme Russ #define THERM_INT_HIGH_ENABLE (1 << 0) 39598568f0fSGraeme Russ #define THERM_INT_LOW_ENABLE (1 << 1) 39698568f0fSGraeme Russ #define THERM_INT_PLN_ENABLE (1 << 24) 39798568f0fSGraeme Russ 39898568f0fSGraeme Russ #define MSR_IA32_THERM_STATUS 0x0000019c 39998568f0fSGraeme Russ 40098568f0fSGraeme Russ #define THERM_STATUS_PROCHOT (1 << 0) 40198568f0fSGraeme Russ #define THERM_STATUS_POWER_LIMIT (1 << 10) 40298568f0fSGraeme Russ 40398568f0fSGraeme Russ #define MSR_THERM2_CTL 0x0000019d 40498568f0fSGraeme Russ 40598568f0fSGraeme Russ #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 40698568f0fSGraeme Russ 40798568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE 0x000001a0 408ede97093SSimon Glass #define H_MISC_DISABLE_TURBO (1 << 6) 40998568f0fSGraeme Russ 41098568f0fSGraeme Russ #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 41198568f0fSGraeme Russ 41298568f0fSGraeme Russ #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 413dc68584bSSimon Glass #define ENERGY_PERF_BIAS_PERFORMANCE 0 414dc68584bSSimon Glass #define ENERGY_PERF_BIAS_NORMAL 6 415dc68584bSSimon Glass #define ENERGY_PERF_BIAS_POWERSAVE 15 41698568f0fSGraeme Russ 41798568f0fSGraeme Russ #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 41898568f0fSGraeme Russ 41998568f0fSGraeme Russ #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 42098568f0fSGraeme Russ #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 42198568f0fSGraeme Russ 42298568f0fSGraeme Russ #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 42398568f0fSGraeme Russ 42498568f0fSGraeme Russ #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 42598568f0fSGraeme Russ #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 42698568f0fSGraeme Russ #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 42798568f0fSGraeme Russ 42898568f0fSGraeme Russ /* Thermal Thresholds Support */ 42998568f0fSGraeme Russ #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 43098568f0fSGraeme Russ #define THERM_SHIFT_THRESHOLD0 8 43198568f0fSGraeme Russ #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 43298568f0fSGraeme Russ #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 43398568f0fSGraeme Russ #define THERM_SHIFT_THRESHOLD1 16 43498568f0fSGraeme Russ #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 43598568f0fSGraeme Russ #define THERM_STATUS_THRESHOLD0 (1 << 6) 43698568f0fSGraeme Russ #define THERM_LOG_THRESHOLD0 (1 << 7) 43798568f0fSGraeme Russ #define THERM_STATUS_THRESHOLD1 (1 << 8) 43898568f0fSGraeme Russ #define THERM_LOG_THRESHOLD1 (1 << 9) 43998568f0fSGraeme Russ 44098568f0fSGraeme Russ /* MISC_ENABLE bits: architectural */ 44198568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0) 44298568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1) 44398568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_EMON (1ULL << 7) 44498568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11) 44598568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12) 44698568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16) 44798568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) 44898568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << 22) 44998568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << 23) 45098568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34) 45198568f0fSGraeme Russ 45298568f0fSGraeme Russ /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 45398568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << 2) 45498568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << 3) 45598568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4) 45698568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << 6) 45798568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << 8) 45898568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << 9) 45998568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_FERR (1ULL << 10) 46098568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << 10) 46198568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << 13) 46298568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << 19) 46398568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << 20) 46498568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << 24) 46598568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << 37) 46698568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38) 46798568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39) 46898568f0fSGraeme Russ 469dc68584bSSimon Glass #define MSR_IA32_TSC_DEADLINE 0x000006E0 470dc68584bSSimon Glass 47198568f0fSGraeme Russ /* P4/Xeon+ specific */ 47298568f0fSGraeme Russ #define MSR_IA32_MCG_EAX 0x00000180 47398568f0fSGraeme Russ #define MSR_IA32_MCG_EBX 0x00000181 47498568f0fSGraeme Russ #define MSR_IA32_MCG_ECX 0x00000182 47598568f0fSGraeme Russ #define MSR_IA32_MCG_EDX 0x00000183 47698568f0fSGraeme Russ #define MSR_IA32_MCG_ESI 0x00000184 47798568f0fSGraeme Russ #define MSR_IA32_MCG_EDI 0x00000185 47898568f0fSGraeme Russ #define MSR_IA32_MCG_EBP 0x00000186 47998568f0fSGraeme Russ #define MSR_IA32_MCG_ESP 0x00000187 48098568f0fSGraeme Russ #define MSR_IA32_MCG_EFLAGS 0x00000188 48198568f0fSGraeme Russ #define MSR_IA32_MCG_EIP 0x00000189 48298568f0fSGraeme Russ #define MSR_IA32_MCG_RESERVED 0x0000018a 48398568f0fSGraeme Russ 48498568f0fSGraeme Russ /* Pentium IV performance counter MSRs */ 48598568f0fSGraeme Russ #define MSR_P4_BPU_PERFCTR0 0x00000300 48698568f0fSGraeme Russ #define MSR_P4_BPU_PERFCTR1 0x00000301 48798568f0fSGraeme Russ #define MSR_P4_BPU_PERFCTR2 0x00000302 48898568f0fSGraeme Russ #define MSR_P4_BPU_PERFCTR3 0x00000303 48998568f0fSGraeme Russ #define MSR_P4_MS_PERFCTR0 0x00000304 49098568f0fSGraeme Russ #define MSR_P4_MS_PERFCTR1 0x00000305 49198568f0fSGraeme Russ #define MSR_P4_MS_PERFCTR2 0x00000306 49298568f0fSGraeme Russ #define MSR_P4_MS_PERFCTR3 0x00000307 49398568f0fSGraeme Russ #define MSR_P4_FLAME_PERFCTR0 0x00000308 49498568f0fSGraeme Russ #define MSR_P4_FLAME_PERFCTR1 0x00000309 49598568f0fSGraeme Russ #define MSR_P4_FLAME_PERFCTR2 0x0000030a 49698568f0fSGraeme Russ #define MSR_P4_FLAME_PERFCTR3 0x0000030b 49798568f0fSGraeme Russ #define MSR_P4_IQ_PERFCTR0 0x0000030c 49898568f0fSGraeme Russ #define MSR_P4_IQ_PERFCTR1 0x0000030d 49998568f0fSGraeme Russ #define MSR_P4_IQ_PERFCTR2 0x0000030e 50098568f0fSGraeme Russ #define MSR_P4_IQ_PERFCTR3 0x0000030f 50198568f0fSGraeme Russ #define MSR_P4_IQ_PERFCTR4 0x00000310 50298568f0fSGraeme Russ #define MSR_P4_IQ_PERFCTR5 0x00000311 50398568f0fSGraeme Russ #define MSR_P4_BPU_CCCR0 0x00000360 50498568f0fSGraeme Russ #define MSR_P4_BPU_CCCR1 0x00000361 50598568f0fSGraeme Russ #define MSR_P4_BPU_CCCR2 0x00000362 50698568f0fSGraeme Russ #define MSR_P4_BPU_CCCR3 0x00000363 50798568f0fSGraeme Russ #define MSR_P4_MS_CCCR0 0x00000364 50898568f0fSGraeme Russ #define MSR_P4_MS_CCCR1 0x00000365 50998568f0fSGraeme Russ #define MSR_P4_MS_CCCR2 0x00000366 51098568f0fSGraeme Russ #define MSR_P4_MS_CCCR3 0x00000367 51198568f0fSGraeme Russ #define MSR_P4_FLAME_CCCR0 0x00000368 51298568f0fSGraeme Russ #define MSR_P4_FLAME_CCCR1 0x00000369 51398568f0fSGraeme Russ #define MSR_P4_FLAME_CCCR2 0x0000036a 51498568f0fSGraeme Russ #define MSR_P4_FLAME_CCCR3 0x0000036b 51598568f0fSGraeme Russ #define MSR_P4_IQ_CCCR0 0x0000036c 51698568f0fSGraeme Russ #define MSR_P4_IQ_CCCR1 0x0000036d 51798568f0fSGraeme Russ #define MSR_P4_IQ_CCCR2 0x0000036e 51898568f0fSGraeme Russ #define MSR_P4_IQ_CCCR3 0x0000036f 51998568f0fSGraeme Russ #define MSR_P4_IQ_CCCR4 0x00000370 52098568f0fSGraeme Russ #define MSR_P4_IQ_CCCR5 0x00000371 52198568f0fSGraeme Russ #define MSR_P4_ALF_ESCR0 0x000003ca 52298568f0fSGraeme Russ #define MSR_P4_ALF_ESCR1 0x000003cb 52398568f0fSGraeme Russ #define MSR_P4_BPU_ESCR0 0x000003b2 52498568f0fSGraeme Russ #define MSR_P4_BPU_ESCR1 0x000003b3 52598568f0fSGraeme Russ #define MSR_P4_BSU_ESCR0 0x000003a0 52698568f0fSGraeme Russ #define MSR_P4_BSU_ESCR1 0x000003a1 52798568f0fSGraeme Russ #define MSR_P4_CRU_ESCR0 0x000003b8 52898568f0fSGraeme Russ #define MSR_P4_CRU_ESCR1 0x000003b9 52998568f0fSGraeme Russ #define MSR_P4_CRU_ESCR2 0x000003cc 53098568f0fSGraeme Russ #define MSR_P4_CRU_ESCR3 0x000003cd 53198568f0fSGraeme Russ #define MSR_P4_CRU_ESCR4 0x000003e0 53298568f0fSGraeme Russ #define MSR_P4_CRU_ESCR5 0x000003e1 53398568f0fSGraeme Russ #define MSR_P4_DAC_ESCR0 0x000003a8 53498568f0fSGraeme Russ #define MSR_P4_DAC_ESCR1 0x000003a9 53598568f0fSGraeme Russ #define MSR_P4_FIRM_ESCR0 0x000003a4 53698568f0fSGraeme Russ #define MSR_P4_FIRM_ESCR1 0x000003a5 53798568f0fSGraeme Russ #define MSR_P4_FLAME_ESCR0 0x000003a6 53898568f0fSGraeme Russ #define MSR_P4_FLAME_ESCR1 0x000003a7 53998568f0fSGraeme Russ #define MSR_P4_FSB_ESCR0 0x000003a2 54098568f0fSGraeme Russ #define MSR_P4_FSB_ESCR1 0x000003a3 54198568f0fSGraeme Russ #define MSR_P4_IQ_ESCR0 0x000003ba 54298568f0fSGraeme Russ #define MSR_P4_IQ_ESCR1 0x000003bb 54398568f0fSGraeme Russ #define MSR_P4_IS_ESCR0 0x000003b4 54498568f0fSGraeme Russ #define MSR_P4_IS_ESCR1 0x000003b5 54598568f0fSGraeme Russ #define MSR_P4_ITLB_ESCR0 0x000003b6 54698568f0fSGraeme Russ #define MSR_P4_ITLB_ESCR1 0x000003b7 54798568f0fSGraeme Russ #define MSR_P4_IX_ESCR0 0x000003c8 54898568f0fSGraeme Russ #define MSR_P4_IX_ESCR1 0x000003c9 54998568f0fSGraeme Russ #define MSR_P4_MOB_ESCR0 0x000003aa 55098568f0fSGraeme Russ #define MSR_P4_MOB_ESCR1 0x000003ab 55198568f0fSGraeme Russ #define MSR_P4_MS_ESCR0 0x000003c0 55298568f0fSGraeme Russ #define MSR_P4_MS_ESCR1 0x000003c1 55398568f0fSGraeme Russ #define MSR_P4_PMH_ESCR0 0x000003ac 55498568f0fSGraeme Russ #define MSR_P4_PMH_ESCR1 0x000003ad 55598568f0fSGraeme Russ #define MSR_P4_RAT_ESCR0 0x000003bc 55698568f0fSGraeme Russ #define MSR_P4_RAT_ESCR1 0x000003bd 55798568f0fSGraeme Russ #define MSR_P4_SAAT_ESCR0 0x000003ae 55898568f0fSGraeme Russ #define MSR_P4_SAAT_ESCR1 0x000003af 55998568f0fSGraeme Russ #define MSR_P4_SSU_ESCR0 0x000003be 56098568f0fSGraeme Russ #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 56198568f0fSGraeme Russ 56298568f0fSGraeme Russ #define MSR_P4_TBPU_ESCR0 0x000003c2 56398568f0fSGraeme Russ #define MSR_P4_TBPU_ESCR1 0x000003c3 56498568f0fSGraeme Russ #define MSR_P4_TC_ESCR0 0x000003c4 56598568f0fSGraeme Russ #define MSR_P4_TC_ESCR1 0x000003c5 56698568f0fSGraeme Russ #define MSR_P4_U2L_ESCR0 0x000003b0 56798568f0fSGraeme Russ #define MSR_P4_U2L_ESCR1 0x000003b1 56898568f0fSGraeme Russ 56998568f0fSGraeme Russ #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 57098568f0fSGraeme Russ 57198568f0fSGraeme Russ /* Intel Core-based CPU performance counters */ 57298568f0fSGraeme Russ #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 57398568f0fSGraeme Russ #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 57498568f0fSGraeme Russ #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 57598568f0fSGraeme Russ #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 57698568f0fSGraeme Russ #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 57798568f0fSGraeme Russ #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 57898568f0fSGraeme Russ #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 57998568f0fSGraeme Russ 58098568f0fSGraeme Russ /* Geode defined MSRs */ 58198568f0fSGraeme Russ #define MSR_GEODE_BUSCONT_CONF0 0x00001900 58298568f0fSGraeme Russ 58398568f0fSGraeme Russ /* Intel VT MSRs */ 58498568f0fSGraeme Russ #define MSR_IA32_VMX_BASIC 0x00000480 58598568f0fSGraeme Russ #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 58698568f0fSGraeme Russ #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 58798568f0fSGraeme Russ #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 58898568f0fSGraeme Russ #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 58998568f0fSGraeme Russ #define MSR_IA32_VMX_MISC 0x00000485 59098568f0fSGraeme Russ #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 59198568f0fSGraeme Russ #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 59298568f0fSGraeme Russ #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 59398568f0fSGraeme Russ #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 59498568f0fSGraeme Russ #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 59598568f0fSGraeme Russ #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 59698568f0fSGraeme Russ #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 597dc68584bSSimon Glass #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 598dc68584bSSimon Glass #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 599dc68584bSSimon Glass #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 600dc68584bSSimon Glass #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 601dc68584bSSimon Glass #define MSR_IA32_VMX_VMFUNC 0x00000491 60298568f0fSGraeme Russ 603dc68584bSSimon Glass /* VMX_BASIC bits and bitmasks */ 604dc68584bSSimon Glass #define VMX_BASIC_VMCS_SIZE_SHIFT 32 605dc68584bSSimon Glass #define VMX_BASIC_64 0x0001000000000000LLU 606dc68584bSSimon Glass #define VMX_BASIC_MEM_TYPE_SHIFT 50 607dc68584bSSimon Glass #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 608dc68584bSSimon Glass #define VMX_BASIC_MEM_TYPE_WB 6LLU 609dc68584bSSimon Glass #define VMX_BASIC_INOUT 0x0040000000000000LLU 610dc68584bSSimon Glass 611dc68584bSSimon Glass /* MSR_IA32_VMX_MISC bits */ 612dc68584bSSimon Glass #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 613dc68584bSSimon Glass #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 61498568f0fSGraeme Russ /* AMD-V MSRs */ 61598568f0fSGraeme Russ 61698568f0fSGraeme Russ #define MSR_VM_CR 0xc0010114 61798568f0fSGraeme Russ #define MSR_VM_IGNNE 0xc0010115 61898568f0fSGraeme Russ #define MSR_VM_HSAVE_PA 0xc0010117 61998568f0fSGraeme Russ 62098568f0fSGraeme Russ #endif /* _ASM_X86_MSR_INDEX_H */ 621