198568f0fSGraeme Russ /* 298568f0fSGraeme Russ * Taken from the linux kernel file of the same name 398568f0fSGraeme Russ * 498568f0fSGraeme Russ * (C) Copyright 2012 598568f0fSGraeme Russ * Graeme Russ, <graeme.russ@gmail.com> 698568f0fSGraeme Russ * 71a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 898568f0fSGraeme Russ */ 998568f0fSGraeme Russ 1098568f0fSGraeme Russ #ifndef _ASM_X86_MSR_INDEX_H 1198568f0fSGraeme Russ #define _ASM_X86_MSR_INDEX_H 1298568f0fSGraeme Russ 1398568f0fSGraeme Russ /* CPU model specific register (MSR) numbers */ 1498568f0fSGraeme Russ 1598568f0fSGraeme Russ /* x86-64 specific MSRs */ 1698568f0fSGraeme Russ #define MSR_EFER 0xc0000080 /* extended feature register */ 1798568f0fSGraeme Russ #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 1898568f0fSGraeme Russ #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 1998568f0fSGraeme Russ #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 2098568f0fSGraeme Russ #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 2198568f0fSGraeme Russ #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 2298568f0fSGraeme Russ #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 2398568f0fSGraeme Russ #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 2498568f0fSGraeme Russ #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 2598568f0fSGraeme Russ 2698568f0fSGraeme Russ /* EFER bits: */ 2798568f0fSGraeme Russ #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 2898568f0fSGraeme Russ #define _EFER_LME 8 /* Long mode enable */ 2998568f0fSGraeme Russ #define _EFER_LMA 10 /* Long mode active (read-only) */ 3098568f0fSGraeme Russ #define _EFER_NX 11 /* No execute enable */ 3198568f0fSGraeme Russ #define _EFER_SVME 12 /* Enable virtualization */ 3298568f0fSGraeme Russ #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 3398568f0fSGraeme Russ #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 3498568f0fSGraeme Russ 3598568f0fSGraeme Russ #define EFER_SCE (1<<_EFER_SCE) 3698568f0fSGraeme Russ #define EFER_LME (1<<_EFER_LME) 3798568f0fSGraeme Russ #define EFER_LMA (1<<_EFER_LMA) 3898568f0fSGraeme Russ #define EFER_NX (1<<_EFER_NX) 3998568f0fSGraeme Russ #define EFER_SVME (1<<_EFER_SVME) 4098568f0fSGraeme Russ #define EFER_LMSLE (1<<_EFER_LMSLE) 4198568f0fSGraeme Russ #define EFER_FFXSR (1<<_EFER_FFXSR) 4298568f0fSGraeme Russ 4398568f0fSGraeme Russ /* Intel MSRs. Some also available on other CPUs */ 4498568f0fSGraeme Russ #define MSR_IA32_PERFCTR0 0x000000c1 4598568f0fSGraeme Russ #define MSR_IA32_PERFCTR1 0x000000c2 4698568f0fSGraeme Russ #define MSR_FSB_FREQ 0x000000cd 47*dc68584bSSimon Glass #define MSR_NHM_PLATFORM_INFO 0x000000ce 4898568f0fSGraeme Russ 4998568f0fSGraeme Russ #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 5098568f0fSGraeme Russ #define NHM_C3_AUTO_DEMOTE (1UL << 25) 5198568f0fSGraeme Russ #define NHM_C1_AUTO_DEMOTE (1UL << 26) 5298568f0fSGraeme Russ #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 53*dc68584bSSimon Glass #define SNB_C1_AUTO_UNDEMOTE (1UL << 27) 54*dc68584bSSimon Glass #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) 5598568f0fSGraeme Russ 56*dc68584bSSimon Glass #define MSR_PLATFORM_INFO 0x000000ce 5798568f0fSGraeme Russ #define MSR_MTRRcap 0x000000fe 5898568f0fSGraeme Russ #define MSR_IA32_BBL_CR_CTL 0x00000119 5998568f0fSGraeme Russ #define MSR_IA32_BBL_CR_CTL3 0x0000011e 6098568f0fSGraeme Russ 6198568f0fSGraeme Russ #define MSR_IA32_SYSENTER_CS 0x00000174 6298568f0fSGraeme Russ #define MSR_IA32_SYSENTER_ESP 0x00000175 6398568f0fSGraeme Russ #define MSR_IA32_SYSENTER_EIP 0x00000176 6498568f0fSGraeme Russ 6598568f0fSGraeme Russ #define MSR_IA32_MCG_CAP 0x00000179 6698568f0fSGraeme Russ #define MSR_IA32_MCG_STATUS 0x0000017a 6798568f0fSGraeme Russ #define MSR_IA32_MCG_CTL 0x0000017b 6898568f0fSGraeme Russ 6998568f0fSGraeme Russ #define MSR_OFFCORE_RSP_0 0x000001a6 7098568f0fSGraeme Russ #define MSR_OFFCORE_RSP_1 0x000001a7 71*dc68584bSSimon Glass #define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad 72*dc68584bSSimon Glass #define MSR_IVT_TURBO_RATIO_LIMIT 0x000001ae 73*dc68584bSSimon Glass 74*dc68584bSSimon Glass #define MSR_LBR_SELECT 0x000001c8 75*dc68584bSSimon Glass #define MSR_LBR_TOS 0x000001c9 76*dc68584bSSimon Glass #define MSR_LBR_NHM_FROM 0x00000680 77*dc68584bSSimon Glass #define MSR_LBR_NHM_TO 0x000006c0 78*dc68584bSSimon Glass #define MSR_LBR_CORE_FROM 0x00000040 79*dc68584bSSimon Glass #define MSR_LBR_CORE_TO 0x00000060 8098568f0fSGraeme Russ 8198568f0fSGraeme Russ #define MSR_IA32_PEBS_ENABLE 0x000003f1 8298568f0fSGraeme Russ #define MSR_IA32_DS_AREA 0x00000600 8398568f0fSGraeme Russ #define MSR_IA32_PERF_CAPABILITIES 0x00000345 84*dc68584bSSimon Glass #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 8598568f0fSGraeme Russ 8698568f0fSGraeme Russ #define MSR_MTRRfix64K_00000 0x00000250 8798568f0fSGraeme Russ #define MSR_MTRRfix16K_80000 0x00000258 8898568f0fSGraeme Russ #define MSR_MTRRfix16K_A0000 0x00000259 8998568f0fSGraeme Russ #define MSR_MTRRfix4K_C0000 0x00000268 9098568f0fSGraeme Russ #define MSR_MTRRfix4K_C8000 0x00000269 9198568f0fSGraeme Russ #define MSR_MTRRfix4K_D0000 0x0000026a 9298568f0fSGraeme Russ #define MSR_MTRRfix4K_D8000 0x0000026b 9398568f0fSGraeme Russ #define MSR_MTRRfix4K_E0000 0x0000026c 9498568f0fSGraeme Russ #define MSR_MTRRfix4K_E8000 0x0000026d 9598568f0fSGraeme Russ #define MSR_MTRRfix4K_F0000 0x0000026e 9698568f0fSGraeme Russ #define MSR_MTRRfix4K_F8000 0x0000026f 9798568f0fSGraeme Russ #define MSR_MTRRdefType 0x000002ff 9898568f0fSGraeme Russ 9998568f0fSGraeme Russ #define MSR_IA32_CR_PAT 0x00000277 10098568f0fSGraeme Russ 10198568f0fSGraeme Russ #define MSR_IA32_DEBUGCTLMSR 0x000001d9 10298568f0fSGraeme Russ #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 10398568f0fSGraeme Russ #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 10498568f0fSGraeme Russ #define MSR_IA32_LASTINTFROMIP 0x000001dd 10598568f0fSGraeme Russ #define MSR_IA32_LASTINTTOIP 0x000001de 10698568f0fSGraeme Russ 10798568f0fSGraeme Russ /* DEBUGCTLMSR bits (others vary by model): */ 108*dc68584bSSimon Glass #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 109*dc68584bSSimon Glass /* single-step on branches */ 11098568f0fSGraeme Russ #define DEBUGCTLMSR_BTF (1UL << 1) 11198568f0fSGraeme Russ #define DEBUGCTLMSR_TR (1UL << 6) 11298568f0fSGraeme Russ #define DEBUGCTLMSR_BTS (1UL << 7) 11398568f0fSGraeme Russ #define DEBUGCTLMSR_BTINT (1UL << 8) 11498568f0fSGraeme Russ #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 11598568f0fSGraeme Russ #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 11698568f0fSGraeme Russ #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 11798568f0fSGraeme Russ 118*dc68584bSSimon Glass #define MSR_IA32_POWER_CTL 0x000001fc 119*dc68584bSSimon Glass 12098568f0fSGraeme Russ #define MSR_IA32_MC0_CTL 0x00000400 12198568f0fSGraeme Russ #define MSR_IA32_MC0_STATUS 0x00000401 12298568f0fSGraeme Russ #define MSR_IA32_MC0_ADDR 0x00000402 12398568f0fSGraeme Russ #define MSR_IA32_MC0_MISC 0x00000403 12498568f0fSGraeme Russ 125*dc68584bSSimon Glass /* C-state Residency Counters */ 126*dc68584bSSimon Glass #define MSR_PKG_C3_RESIDENCY 0x000003f8 127*dc68584bSSimon Glass #define MSR_PKG_C6_RESIDENCY 0x000003f9 128*dc68584bSSimon Glass #define MSR_PKG_C7_RESIDENCY 0x000003fa 129*dc68584bSSimon Glass #define MSR_CORE_C3_RESIDENCY 0x000003fc 130*dc68584bSSimon Glass #define MSR_CORE_C6_RESIDENCY 0x000003fd 131*dc68584bSSimon Glass #define MSR_CORE_C7_RESIDENCY 0x000003fe 132*dc68584bSSimon Glass #define MSR_PKG_C2_RESIDENCY 0x0000060d 133*dc68584bSSimon Glass #define MSR_PKG_C8_RESIDENCY 0x00000630 134*dc68584bSSimon Glass #define MSR_PKG_C9_RESIDENCY 0x00000631 135*dc68584bSSimon Glass #define MSR_PKG_C10_RESIDENCY 0x00000632 136*dc68584bSSimon Glass 137*dc68584bSSimon Glass /* Run Time Average Power Limiting (RAPL) Interface */ 138*dc68584bSSimon Glass 139*dc68584bSSimon Glass #define MSR_RAPL_POWER_UNIT 0x00000606 140*dc68584bSSimon Glass 141*dc68584bSSimon Glass #define MSR_PKG_POWER_LIMIT 0x00000610 142*dc68584bSSimon Glass #define MSR_PKG_ENERGY_STATUS 0x00000611 143*dc68584bSSimon Glass #define MSR_PKG_PERF_STATUS 0x00000613 144*dc68584bSSimon Glass #define MSR_PKG_POWER_INFO 0x00000614 145*dc68584bSSimon Glass 146*dc68584bSSimon Glass #define MSR_DRAM_POWER_LIMIT 0x00000618 147*dc68584bSSimon Glass #define MSR_DRAM_ENERGY_STATUS 0x00000619 148*dc68584bSSimon Glass #define MSR_DRAM_PERF_STATUS 0x0000061b 149*dc68584bSSimon Glass #define MSR_DRAM_POWER_INFO 0x0000061c 150*dc68584bSSimon Glass 151*dc68584bSSimon Glass #define MSR_PP0_POWER_LIMIT 0x00000638 152*dc68584bSSimon Glass #define MSR_PP0_ENERGY_STATUS 0x00000639 153*dc68584bSSimon Glass #define MSR_PP0_POLICY 0x0000063a 154*dc68584bSSimon Glass #define MSR_PP0_PERF_STATUS 0x0000063b 155*dc68584bSSimon Glass 156*dc68584bSSimon Glass #define MSR_PP1_POWER_LIMIT 0x00000640 157*dc68584bSSimon Glass #define MSR_PP1_ENERGY_STATUS 0x00000641 158*dc68584bSSimon Glass #define MSR_PP1_POLICY 0x00000642 159*dc68584bSSimon Glass 160*dc68584bSSimon Glass #define MSR_CORE_C1_RES 0x00000660 161*dc68584bSSimon Glass 16298568f0fSGraeme Russ #define MSR_AMD64_MC0_MASK 0xc0010044 16398568f0fSGraeme Russ 16498568f0fSGraeme Russ #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 16598568f0fSGraeme Russ #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 16698568f0fSGraeme Russ #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 16798568f0fSGraeme Russ #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 16898568f0fSGraeme Russ 16998568f0fSGraeme Russ #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 17098568f0fSGraeme Russ 17198568f0fSGraeme Russ /* These are consecutive and not in the normal 4er MCE bank block */ 17298568f0fSGraeme Russ #define MSR_IA32_MC0_CTL2 0x00000280 17398568f0fSGraeme Russ #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 17498568f0fSGraeme Russ 17598568f0fSGraeme Russ #define MSR_P6_PERFCTR0 0x000000c1 17698568f0fSGraeme Russ #define MSR_P6_PERFCTR1 0x000000c2 17798568f0fSGraeme Russ #define MSR_P6_EVNTSEL0 0x00000186 17898568f0fSGraeme Russ #define MSR_P6_EVNTSEL1 0x00000187 17998568f0fSGraeme Russ 180*dc68584bSSimon Glass #define MSR_KNC_PERFCTR0 0x00000020 181*dc68584bSSimon Glass #define MSR_KNC_PERFCTR1 0x00000021 182*dc68584bSSimon Glass #define MSR_KNC_EVNTSEL0 0x00000028 183*dc68584bSSimon Glass #define MSR_KNC_EVNTSEL1 0x00000029 184*dc68584bSSimon Glass 185*dc68584bSSimon Glass /* Alternative perfctr range with full access. */ 186*dc68584bSSimon Glass #define MSR_IA32_PMC0 0x000004c1 187*dc68584bSSimon Glass 18898568f0fSGraeme Russ /* AMD64 MSRs. Not complete. See the architecture manual for a more 18998568f0fSGraeme Russ complete list. */ 19098568f0fSGraeme Russ 19198568f0fSGraeme Russ #define MSR_AMD64_PATCH_LEVEL 0x0000008b 192*dc68584bSSimon Glass #define MSR_AMD64_TSC_RATIO 0xc0000104 19398568f0fSGraeme Russ #define MSR_AMD64_NB_CFG 0xc001001f 19498568f0fSGraeme Russ #define MSR_AMD64_PATCH_LOADER 0xc0010020 19598568f0fSGraeme Russ #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 19698568f0fSGraeme Russ #define MSR_AMD64_OSVW_STATUS 0xc0010141 197*dc68584bSSimon Glass #define MSR_AMD64_LS_CFG 0xc0011020 19898568f0fSGraeme Russ #define MSR_AMD64_DC_CFG 0xc0011022 199*dc68584bSSimon Glass #define MSR_AMD64_BU_CFG2 0xc001102a 20098568f0fSGraeme Russ #define MSR_AMD64_IBSFETCHCTL 0xc0011030 20198568f0fSGraeme Russ #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 20298568f0fSGraeme Russ #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 203*dc68584bSSimon Glass #define MSR_AMD64_IBSFETCH_REG_COUNT 3 204*dc68584bSSimon Glass #define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 20598568f0fSGraeme Russ #define MSR_AMD64_IBSOPCTL 0xc0011033 20698568f0fSGraeme Russ #define MSR_AMD64_IBSOPRIP 0xc0011034 20798568f0fSGraeme Russ #define MSR_AMD64_IBSOPDATA 0xc0011035 20898568f0fSGraeme Russ #define MSR_AMD64_IBSOPDATA2 0xc0011036 20998568f0fSGraeme Russ #define MSR_AMD64_IBSOPDATA3 0xc0011037 21098568f0fSGraeme Russ #define MSR_AMD64_IBSDCLINAD 0xc0011038 21198568f0fSGraeme Russ #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 212*dc68584bSSimon Glass #define MSR_AMD64_IBSOP_REG_COUNT 7 213*dc68584bSSimon Glass #define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 21498568f0fSGraeme Russ #define MSR_AMD64_IBSCTL 0xc001103a 21598568f0fSGraeme Russ #define MSR_AMD64_IBSBRTARGET 0xc001103b 216*dc68584bSSimon Glass #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 217*dc68584bSSimon Glass 218*dc68584bSSimon Glass /* Fam 16h MSRs */ 219*dc68584bSSimon Glass #define MSR_F16H_L2I_PERF_CTL 0xc0010230 220*dc68584bSSimon Glass #define MSR_F16H_L2I_PERF_CTR 0xc0010231 22198568f0fSGraeme Russ 22298568f0fSGraeme Russ /* Fam 15h MSRs */ 22398568f0fSGraeme Russ #define MSR_F15H_PERF_CTL 0xc0010200 22498568f0fSGraeme Russ #define MSR_F15H_PERF_CTR 0xc0010201 225*dc68584bSSimon Glass #define MSR_F15H_NB_PERF_CTL 0xc0010240 226*dc68584bSSimon Glass #define MSR_F15H_NB_PERF_CTR 0xc0010241 22798568f0fSGraeme Russ 22898568f0fSGraeme Russ /* Fam 10h MSRs */ 22998568f0fSGraeme Russ #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 23098568f0fSGraeme Russ #define FAM10H_MMIO_CONF_ENABLE (1<<0) 23198568f0fSGraeme Russ #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 23298568f0fSGraeme Russ #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 23398568f0fSGraeme Russ #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 23498568f0fSGraeme Russ #define FAM10H_MMIO_CONF_BASE_SHIFT 20 23598568f0fSGraeme Russ #define MSR_FAM10H_NODE_ID 0xc001100c 23698568f0fSGraeme Russ 23798568f0fSGraeme Russ /* K8 MSRs */ 23898568f0fSGraeme Russ #define MSR_K8_TOP_MEM1 0xc001001a 23998568f0fSGraeme Russ #define MSR_K8_TOP_MEM2 0xc001001d 24098568f0fSGraeme Russ #define MSR_K8_SYSCFG 0xc0010010 24198568f0fSGraeme Russ #define MSR_K8_INT_PENDING_MSG 0xc0010055 24298568f0fSGraeme Russ /* C1E active bits in int pending message */ 24398568f0fSGraeme Russ #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 24498568f0fSGraeme Russ #define MSR_K8_TSEG_ADDR 0xc0010112 24598568f0fSGraeme Russ #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 24698568f0fSGraeme Russ #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 24798568f0fSGraeme Russ #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 24898568f0fSGraeme Russ 24998568f0fSGraeme Russ /* K7 MSRs */ 25098568f0fSGraeme Russ #define MSR_K7_EVNTSEL0 0xc0010000 25198568f0fSGraeme Russ #define MSR_K7_PERFCTR0 0xc0010004 25298568f0fSGraeme Russ #define MSR_K7_EVNTSEL1 0xc0010001 25398568f0fSGraeme Russ #define MSR_K7_PERFCTR1 0xc0010005 25498568f0fSGraeme Russ #define MSR_K7_EVNTSEL2 0xc0010002 25598568f0fSGraeme Russ #define MSR_K7_PERFCTR2 0xc0010006 25698568f0fSGraeme Russ #define MSR_K7_EVNTSEL3 0xc0010003 25798568f0fSGraeme Russ #define MSR_K7_PERFCTR3 0xc0010007 25898568f0fSGraeme Russ #define MSR_K7_CLK_CTL 0xc001001b 25998568f0fSGraeme Russ #define MSR_K7_HWCR 0xc0010015 26098568f0fSGraeme Russ #define MSR_K7_FID_VID_CTL 0xc0010041 26198568f0fSGraeme Russ #define MSR_K7_FID_VID_STATUS 0xc0010042 26298568f0fSGraeme Russ 26398568f0fSGraeme Russ /* K6 MSRs */ 26498568f0fSGraeme Russ #define MSR_K6_WHCR 0xc0000082 26598568f0fSGraeme Russ #define MSR_K6_UWCCR 0xc0000085 26698568f0fSGraeme Russ #define MSR_K6_EPMR 0xc0000086 26798568f0fSGraeme Russ #define MSR_K6_PSOR 0xc0000087 26898568f0fSGraeme Russ #define MSR_K6_PFIR 0xc0000088 26998568f0fSGraeme Russ 27098568f0fSGraeme Russ /* Centaur-Hauls/IDT defined MSRs. */ 27198568f0fSGraeme Russ #define MSR_IDT_FCR1 0x00000107 27298568f0fSGraeme Russ #define MSR_IDT_FCR2 0x00000108 27398568f0fSGraeme Russ #define MSR_IDT_FCR3 0x00000109 27498568f0fSGraeme Russ #define MSR_IDT_FCR4 0x0000010a 27598568f0fSGraeme Russ 27698568f0fSGraeme Russ #define MSR_IDT_MCR0 0x00000110 27798568f0fSGraeme Russ #define MSR_IDT_MCR1 0x00000111 27898568f0fSGraeme Russ #define MSR_IDT_MCR2 0x00000112 27998568f0fSGraeme Russ #define MSR_IDT_MCR3 0x00000113 28098568f0fSGraeme Russ #define MSR_IDT_MCR4 0x00000114 28198568f0fSGraeme Russ #define MSR_IDT_MCR5 0x00000115 28298568f0fSGraeme Russ #define MSR_IDT_MCR6 0x00000116 28398568f0fSGraeme Russ #define MSR_IDT_MCR7 0x00000117 28498568f0fSGraeme Russ #define MSR_IDT_MCR_CTRL 0x00000120 28598568f0fSGraeme Russ 28698568f0fSGraeme Russ /* VIA Cyrix defined MSRs*/ 28798568f0fSGraeme Russ #define MSR_VIA_FCR 0x00001107 28898568f0fSGraeme Russ #define MSR_VIA_LONGHAUL 0x0000110a 28998568f0fSGraeme Russ #define MSR_VIA_RNG 0x0000110b 29098568f0fSGraeme Russ #define MSR_VIA_BCR2 0x00001147 29198568f0fSGraeme Russ 29298568f0fSGraeme Russ /* Transmeta defined MSRs */ 29398568f0fSGraeme Russ #define MSR_TMTA_LONGRUN_CTRL 0x80868010 29498568f0fSGraeme Russ #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 29598568f0fSGraeme Russ #define MSR_TMTA_LRTI_READOUT 0x80868018 29698568f0fSGraeme Russ #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 29798568f0fSGraeme Russ 29898568f0fSGraeme Russ /* Intel defined MSRs. */ 29998568f0fSGraeme Russ #define MSR_IA32_P5_MC_ADDR 0x00000000 30098568f0fSGraeme Russ #define MSR_IA32_P5_MC_TYPE 0x00000001 30198568f0fSGraeme Russ #define MSR_IA32_TSC 0x00000010 30298568f0fSGraeme Russ #define MSR_IA32_PLATFORM_ID 0x00000017 30398568f0fSGraeme Russ #define MSR_IA32_EBL_CR_POWERON 0x0000002a 30498568f0fSGraeme Russ #define MSR_EBC_FREQUENCY_ID 0x0000002c 305*dc68584bSSimon Glass #define MSR_SMI_COUNT 0x00000034 30698568f0fSGraeme Russ #define MSR_IA32_FEATURE_CONTROL 0x0000003a 307*dc68584bSSimon Glass #define MSR_IA32_TSC_ADJUST 0x0000003b 30898568f0fSGraeme Russ 30998568f0fSGraeme Russ #define FEATURE_CONTROL_LOCKED (1<<0) 31098568f0fSGraeme Russ #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) 31198568f0fSGraeme Russ #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 31298568f0fSGraeme Russ 31398568f0fSGraeme Russ #define MSR_IA32_APICBASE 0x0000001b 31498568f0fSGraeme Russ #define MSR_IA32_APICBASE_BSP (1<<8) 31598568f0fSGraeme Russ #define MSR_IA32_APICBASE_ENABLE (1<<11) 31698568f0fSGraeme Russ #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 31798568f0fSGraeme Russ 318*dc68584bSSimon Glass #define MSR_IA32_TSCDEADLINE 0x000006e0 319*dc68584bSSimon Glass 32098568f0fSGraeme Russ #define MSR_IA32_UCODE_WRITE 0x00000079 32198568f0fSGraeme Russ #define MSR_IA32_UCODE_REV 0x0000008b 32298568f0fSGraeme Russ 32398568f0fSGraeme Russ #define MSR_IA32_PERF_STATUS 0x00000198 32498568f0fSGraeme Russ #define MSR_IA32_PERF_CTL 0x00000199 325*dc68584bSSimon Glass #define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 326*dc68584bSSimon Glass #define MSR_AMD_PERF_STATUS 0xc0010063 327*dc68584bSSimon Glass #define MSR_AMD_PERF_CTL 0xc0010062 32898568f0fSGraeme Russ 32998568f0fSGraeme Russ #define MSR_IA32_MPERF 0x000000e7 33098568f0fSGraeme Russ #define MSR_IA32_APERF 0x000000e8 33198568f0fSGraeme Russ 33298568f0fSGraeme Russ #define MSR_IA32_THERM_CONTROL 0x0000019a 33398568f0fSGraeme Russ #define MSR_IA32_THERM_INTERRUPT 0x0000019b 33498568f0fSGraeme Russ 33598568f0fSGraeme Russ #define THERM_INT_HIGH_ENABLE (1 << 0) 33698568f0fSGraeme Russ #define THERM_INT_LOW_ENABLE (1 << 1) 33798568f0fSGraeme Russ #define THERM_INT_PLN_ENABLE (1 << 24) 33898568f0fSGraeme Russ 33998568f0fSGraeme Russ #define MSR_IA32_THERM_STATUS 0x0000019c 34098568f0fSGraeme Russ 34198568f0fSGraeme Russ #define THERM_STATUS_PROCHOT (1 << 0) 34298568f0fSGraeme Russ #define THERM_STATUS_POWER_LIMIT (1 << 10) 34398568f0fSGraeme Russ 34498568f0fSGraeme Russ #define MSR_THERM2_CTL 0x0000019d 34598568f0fSGraeme Russ 34698568f0fSGraeme Russ #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 34798568f0fSGraeme Russ 34898568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE 0x000001a0 34998568f0fSGraeme Russ 35098568f0fSGraeme Russ #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 35198568f0fSGraeme Russ 35298568f0fSGraeme Russ #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 353*dc68584bSSimon Glass #define ENERGY_PERF_BIAS_PERFORMANCE 0 354*dc68584bSSimon Glass #define ENERGY_PERF_BIAS_NORMAL 6 355*dc68584bSSimon Glass #define ENERGY_PERF_BIAS_POWERSAVE 15 35698568f0fSGraeme Russ 35798568f0fSGraeme Russ #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 35898568f0fSGraeme Russ 35998568f0fSGraeme Russ #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 36098568f0fSGraeme Russ #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 36198568f0fSGraeme Russ 36298568f0fSGraeme Russ #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 36398568f0fSGraeme Russ 36498568f0fSGraeme Russ #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 36598568f0fSGraeme Russ #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 36698568f0fSGraeme Russ #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 36798568f0fSGraeme Russ 36898568f0fSGraeme Russ /* Thermal Thresholds Support */ 36998568f0fSGraeme Russ #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 37098568f0fSGraeme Russ #define THERM_SHIFT_THRESHOLD0 8 37198568f0fSGraeme Russ #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 37298568f0fSGraeme Russ #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 37398568f0fSGraeme Russ #define THERM_SHIFT_THRESHOLD1 16 37498568f0fSGraeme Russ #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 37598568f0fSGraeme Russ #define THERM_STATUS_THRESHOLD0 (1 << 6) 37698568f0fSGraeme Russ #define THERM_LOG_THRESHOLD0 (1 << 7) 37798568f0fSGraeme Russ #define THERM_STATUS_THRESHOLD1 (1 << 8) 37898568f0fSGraeme Russ #define THERM_LOG_THRESHOLD1 (1 << 9) 37998568f0fSGraeme Russ 38098568f0fSGraeme Russ /* MISC_ENABLE bits: architectural */ 38198568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0) 38298568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1) 38398568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_EMON (1ULL << 7) 38498568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11) 38598568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12) 38698568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16) 38798568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) 38898568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << 22) 38998568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << 23) 39098568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34) 39198568f0fSGraeme Russ 39298568f0fSGraeme Russ /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 39398568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << 2) 39498568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << 3) 39598568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4) 39698568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << 6) 39798568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << 8) 39898568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << 9) 39998568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_FERR (1ULL << 10) 40098568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << 10) 40198568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << 13) 40298568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << 19) 40398568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << 20) 40498568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << 24) 40598568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << 37) 40698568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38) 40798568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39) 40898568f0fSGraeme Russ 409*dc68584bSSimon Glass #define MSR_IA32_TSC_DEADLINE 0x000006E0 410*dc68584bSSimon Glass 41198568f0fSGraeme Russ /* P4/Xeon+ specific */ 41298568f0fSGraeme Russ #define MSR_IA32_MCG_EAX 0x00000180 41398568f0fSGraeme Russ #define MSR_IA32_MCG_EBX 0x00000181 41498568f0fSGraeme Russ #define MSR_IA32_MCG_ECX 0x00000182 41598568f0fSGraeme Russ #define MSR_IA32_MCG_EDX 0x00000183 41698568f0fSGraeme Russ #define MSR_IA32_MCG_ESI 0x00000184 41798568f0fSGraeme Russ #define MSR_IA32_MCG_EDI 0x00000185 41898568f0fSGraeme Russ #define MSR_IA32_MCG_EBP 0x00000186 41998568f0fSGraeme Russ #define MSR_IA32_MCG_ESP 0x00000187 42098568f0fSGraeme Russ #define MSR_IA32_MCG_EFLAGS 0x00000188 42198568f0fSGraeme Russ #define MSR_IA32_MCG_EIP 0x00000189 42298568f0fSGraeme Russ #define MSR_IA32_MCG_RESERVED 0x0000018a 42398568f0fSGraeme Russ 42498568f0fSGraeme Russ /* Pentium IV performance counter MSRs */ 42598568f0fSGraeme Russ #define MSR_P4_BPU_PERFCTR0 0x00000300 42698568f0fSGraeme Russ #define MSR_P4_BPU_PERFCTR1 0x00000301 42798568f0fSGraeme Russ #define MSR_P4_BPU_PERFCTR2 0x00000302 42898568f0fSGraeme Russ #define MSR_P4_BPU_PERFCTR3 0x00000303 42998568f0fSGraeme Russ #define MSR_P4_MS_PERFCTR0 0x00000304 43098568f0fSGraeme Russ #define MSR_P4_MS_PERFCTR1 0x00000305 43198568f0fSGraeme Russ #define MSR_P4_MS_PERFCTR2 0x00000306 43298568f0fSGraeme Russ #define MSR_P4_MS_PERFCTR3 0x00000307 43398568f0fSGraeme Russ #define MSR_P4_FLAME_PERFCTR0 0x00000308 43498568f0fSGraeme Russ #define MSR_P4_FLAME_PERFCTR1 0x00000309 43598568f0fSGraeme Russ #define MSR_P4_FLAME_PERFCTR2 0x0000030a 43698568f0fSGraeme Russ #define MSR_P4_FLAME_PERFCTR3 0x0000030b 43798568f0fSGraeme Russ #define MSR_P4_IQ_PERFCTR0 0x0000030c 43898568f0fSGraeme Russ #define MSR_P4_IQ_PERFCTR1 0x0000030d 43998568f0fSGraeme Russ #define MSR_P4_IQ_PERFCTR2 0x0000030e 44098568f0fSGraeme Russ #define MSR_P4_IQ_PERFCTR3 0x0000030f 44198568f0fSGraeme Russ #define MSR_P4_IQ_PERFCTR4 0x00000310 44298568f0fSGraeme Russ #define MSR_P4_IQ_PERFCTR5 0x00000311 44398568f0fSGraeme Russ #define MSR_P4_BPU_CCCR0 0x00000360 44498568f0fSGraeme Russ #define MSR_P4_BPU_CCCR1 0x00000361 44598568f0fSGraeme Russ #define MSR_P4_BPU_CCCR2 0x00000362 44698568f0fSGraeme Russ #define MSR_P4_BPU_CCCR3 0x00000363 44798568f0fSGraeme Russ #define MSR_P4_MS_CCCR0 0x00000364 44898568f0fSGraeme Russ #define MSR_P4_MS_CCCR1 0x00000365 44998568f0fSGraeme Russ #define MSR_P4_MS_CCCR2 0x00000366 45098568f0fSGraeme Russ #define MSR_P4_MS_CCCR3 0x00000367 45198568f0fSGraeme Russ #define MSR_P4_FLAME_CCCR0 0x00000368 45298568f0fSGraeme Russ #define MSR_P4_FLAME_CCCR1 0x00000369 45398568f0fSGraeme Russ #define MSR_P4_FLAME_CCCR2 0x0000036a 45498568f0fSGraeme Russ #define MSR_P4_FLAME_CCCR3 0x0000036b 45598568f0fSGraeme Russ #define MSR_P4_IQ_CCCR0 0x0000036c 45698568f0fSGraeme Russ #define MSR_P4_IQ_CCCR1 0x0000036d 45798568f0fSGraeme Russ #define MSR_P4_IQ_CCCR2 0x0000036e 45898568f0fSGraeme Russ #define MSR_P4_IQ_CCCR3 0x0000036f 45998568f0fSGraeme Russ #define MSR_P4_IQ_CCCR4 0x00000370 46098568f0fSGraeme Russ #define MSR_P4_IQ_CCCR5 0x00000371 46198568f0fSGraeme Russ #define MSR_P4_ALF_ESCR0 0x000003ca 46298568f0fSGraeme Russ #define MSR_P4_ALF_ESCR1 0x000003cb 46398568f0fSGraeme Russ #define MSR_P4_BPU_ESCR0 0x000003b2 46498568f0fSGraeme Russ #define MSR_P4_BPU_ESCR1 0x000003b3 46598568f0fSGraeme Russ #define MSR_P4_BSU_ESCR0 0x000003a0 46698568f0fSGraeme Russ #define MSR_P4_BSU_ESCR1 0x000003a1 46798568f0fSGraeme Russ #define MSR_P4_CRU_ESCR0 0x000003b8 46898568f0fSGraeme Russ #define MSR_P4_CRU_ESCR1 0x000003b9 46998568f0fSGraeme Russ #define MSR_P4_CRU_ESCR2 0x000003cc 47098568f0fSGraeme Russ #define MSR_P4_CRU_ESCR3 0x000003cd 47198568f0fSGraeme Russ #define MSR_P4_CRU_ESCR4 0x000003e0 47298568f0fSGraeme Russ #define MSR_P4_CRU_ESCR5 0x000003e1 47398568f0fSGraeme Russ #define MSR_P4_DAC_ESCR0 0x000003a8 47498568f0fSGraeme Russ #define MSR_P4_DAC_ESCR1 0x000003a9 47598568f0fSGraeme Russ #define MSR_P4_FIRM_ESCR0 0x000003a4 47698568f0fSGraeme Russ #define MSR_P4_FIRM_ESCR1 0x000003a5 47798568f0fSGraeme Russ #define MSR_P4_FLAME_ESCR0 0x000003a6 47898568f0fSGraeme Russ #define MSR_P4_FLAME_ESCR1 0x000003a7 47998568f0fSGraeme Russ #define MSR_P4_FSB_ESCR0 0x000003a2 48098568f0fSGraeme Russ #define MSR_P4_FSB_ESCR1 0x000003a3 48198568f0fSGraeme Russ #define MSR_P4_IQ_ESCR0 0x000003ba 48298568f0fSGraeme Russ #define MSR_P4_IQ_ESCR1 0x000003bb 48398568f0fSGraeme Russ #define MSR_P4_IS_ESCR0 0x000003b4 48498568f0fSGraeme Russ #define MSR_P4_IS_ESCR1 0x000003b5 48598568f0fSGraeme Russ #define MSR_P4_ITLB_ESCR0 0x000003b6 48698568f0fSGraeme Russ #define MSR_P4_ITLB_ESCR1 0x000003b7 48798568f0fSGraeme Russ #define MSR_P4_IX_ESCR0 0x000003c8 48898568f0fSGraeme Russ #define MSR_P4_IX_ESCR1 0x000003c9 48998568f0fSGraeme Russ #define MSR_P4_MOB_ESCR0 0x000003aa 49098568f0fSGraeme Russ #define MSR_P4_MOB_ESCR1 0x000003ab 49198568f0fSGraeme Russ #define MSR_P4_MS_ESCR0 0x000003c0 49298568f0fSGraeme Russ #define MSR_P4_MS_ESCR1 0x000003c1 49398568f0fSGraeme Russ #define MSR_P4_PMH_ESCR0 0x000003ac 49498568f0fSGraeme Russ #define MSR_P4_PMH_ESCR1 0x000003ad 49598568f0fSGraeme Russ #define MSR_P4_RAT_ESCR0 0x000003bc 49698568f0fSGraeme Russ #define MSR_P4_RAT_ESCR1 0x000003bd 49798568f0fSGraeme Russ #define MSR_P4_SAAT_ESCR0 0x000003ae 49898568f0fSGraeme Russ #define MSR_P4_SAAT_ESCR1 0x000003af 49998568f0fSGraeme Russ #define MSR_P4_SSU_ESCR0 0x000003be 50098568f0fSGraeme Russ #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 50198568f0fSGraeme Russ 50298568f0fSGraeme Russ #define MSR_P4_TBPU_ESCR0 0x000003c2 50398568f0fSGraeme Russ #define MSR_P4_TBPU_ESCR1 0x000003c3 50498568f0fSGraeme Russ #define MSR_P4_TC_ESCR0 0x000003c4 50598568f0fSGraeme Russ #define MSR_P4_TC_ESCR1 0x000003c5 50698568f0fSGraeme Russ #define MSR_P4_U2L_ESCR0 0x000003b0 50798568f0fSGraeme Russ #define MSR_P4_U2L_ESCR1 0x000003b1 50898568f0fSGraeme Russ 50998568f0fSGraeme Russ #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 51098568f0fSGraeme Russ 51198568f0fSGraeme Russ /* Intel Core-based CPU performance counters */ 51298568f0fSGraeme Russ #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 51398568f0fSGraeme Russ #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 51498568f0fSGraeme Russ #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 51598568f0fSGraeme Russ #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 51698568f0fSGraeme Russ #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 51798568f0fSGraeme Russ #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 51898568f0fSGraeme Russ #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 51998568f0fSGraeme Russ 52098568f0fSGraeme Russ /* Geode defined MSRs */ 52198568f0fSGraeme Russ #define MSR_GEODE_BUSCONT_CONF0 0x00001900 52298568f0fSGraeme Russ 52398568f0fSGraeme Russ /* Intel VT MSRs */ 52498568f0fSGraeme Russ #define MSR_IA32_VMX_BASIC 0x00000480 52598568f0fSGraeme Russ #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 52698568f0fSGraeme Russ #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 52798568f0fSGraeme Russ #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 52898568f0fSGraeme Russ #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 52998568f0fSGraeme Russ #define MSR_IA32_VMX_MISC 0x00000485 53098568f0fSGraeme Russ #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 53198568f0fSGraeme Russ #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 53298568f0fSGraeme Russ #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 53398568f0fSGraeme Russ #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 53498568f0fSGraeme Russ #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 53598568f0fSGraeme Russ #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 53698568f0fSGraeme Russ #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 537*dc68584bSSimon Glass #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 538*dc68584bSSimon Glass #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 539*dc68584bSSimon Glass #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 540*dc68584bSSimon Glass #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 541*dc68584bSSimon Glass #define MSR_IA32_VMX_VMFUNC 0x00000491 54298568f0fSGraeme Russ 543*dc68584bSSimon Glass /* VMX_BASIC bits and bitmasks */ 544*dc68584bSSimon Glass #define VMX_BASIC_VMCS_SIZE_SHIFT 32 545*dc68584bSSimon Glass #define VMX_BASIC_64 0x0001000000000000LLU 546*dc68584bSSimon Glass #define VMX_BASIC_MEM_TYPE_SHIFT 50 547*dc68584bSSimon Glass #define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 548*dc68584bSSimon Glass #define VMX_BASIC_MEM_TYPE_WB 6LLU 549*dc68584bSSimon Glass #define VMX_BASIC_INOUT 0x0040000000000000LLU 550*dc68584bSSimon Glass 551*dc68584bSSimon Glass /* MSR_IA32_VMX_MISC bits */ 552*dc68584bSSimon Glass #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 553*dc68584bSSimon Glass #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 55498568f0fSGraeme Russ /* AMD-V MSRs */ 55598568f0fSGraeme Russ 55698568f0fSGraeme Russ #define MSR_VM_CR 0xc0010114 55798568f0fSGraeme Russ #define MSR_VM_IGNNE 0xc0010115 55898568f0fSGraeme Russ #define MSR_VM_HSAVE_PA 0xc0010117 55998568f0fSGraeme Russ 56098568f0fSGraeme Russ #endif /* _ASM_X86_MSR_INDEX_H */ 561