1*98568f0fSGraeme Russ /* 2*98568f0fSGraeme Russ * Taken from the linux kernel file of the same name 3*98568f0fSGraeme Russ * 4*98568f0fSGraeme Russ * (C) Copyright 2012 5*98568f0fSGraeme Russ * Graeme Russ, <graeme.russ@gmail.com> 6*98568f0fSGraeme Russ * 7*98568f0fSGraeme Russ * This program is free software; you can redistribute it and/or 8*98568f0fSGraeme Russ * modify it under the terms of the GNU General Public License as 9*98568f0fSGraeme Russ * published by the Free Software Foundation; either version 2 of 10*98568f0fSGraeme Russ * the License, or (at your option) any later version. 11*98568f0fSGraeme Russ * 12*98568f0fSGraeme Russ * This program is distributed in the hope that it will be useful, 13*98568f0fSGraeme Russ * but WITHOUT ANY WARRANTY; without even the implied warranty of 14*98568f0fSGraeme Russ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15*98568f0fSGraeme Russ * GNU General Public License for more details. 16*98568f0fSGraeme Russ * 17*98568f0fSGraeme Russ * You should have received a copy of the GNU General Public License 18*98568f0fSGraeme Russ * along with this program; if not, write to the Free Software 19*98568f0fSGraeme Russ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20*98568f0fSGraeme Russ * MA 02111-1307 USA 21*98568f0fSGraeme Russ */ 22*98568f0fSGraeme Russ 23*98568f0fSGraeme Russ #ifndef _ASM_X86_MSR_INDEX_H 24*98568f0fSGraeme Russ #define _ASM_X86_MSR_INDEX_H 25*98568f0fSGraeme Russ 26*98568f0fSGraeme Russ /* CPU model specific register (MSR) numbers */ 27*98568f0fSGraeme Russ 28*98568f0fSGraeme Russ /* x86-64 specific MSRs */ 29*98568f0fSGraeme Russ #define MSR_EFER 0xc0000080 /* extended feature register */ 30*98568f0fSGraeme Russ #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 31*98568f0fSGraeme Russ #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 32*98568f0fSGraeme Russ #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 33*98568f0fSGraeme Russ #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 34*98568f0fSGraeme Russ #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 35*98568f0fSGraeme Russ #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 36*98568f0fSGraeme Russ #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 37*98568f0fSGraeme Russ #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 38*98568f0fSGraeme Russ 39*98568f0fSGraeme Russ /* EFER bits: */ 40*98568f0fSGraeme Russ #define _EFER_SCE 0 /* SYSCALL/SYSRET */ 41*98568f0fSGraeme Russ #define _EFER_LME 8 /* Long mode enable */ 42*98568f0fSGraeme Russ #define _EFER_LMA 10 /* Long mode active (read-only) */ 43*98568f0fSGraeme Russ #define _EFER_NX 11 /* No execute enable */ 44*98568f0fSGraeme Russ #define _EFER_SVME 12 /* Enable virtualization */ 45*98568f0fSGraeme Russ #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 46*98568f0fSGraeme Russ #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 47*98568f0fSGraeme Russ 48*98568f0fSGraeme Russ #define EFER_SCE (1<<_EFER_SCE) 49*98568f0fSGraeme Russ #define EFER_LME (1<<_EFER_LME) 50*98568f0fSGraeme Russ #define EFER_LMA (1<<_EFER_LMA) 51*98568f0fSGraeme Russ #define EFER_NX (1<<_EFER_NX) 52*98568f0fSGraeme Russ #define EFER_SVME (1<<_EFER_SVME) 53*98568f0fSGraeme Russ #define EFER_LMSLE (1<<_EFER_LMSLE) 54*98568f0fSGraeme Russ #define EFER_FFXSR (1<<_EFER_FFXSR) 55*98568f0fSGraeme Russ 56*98568f0fSGraeme Russ /* Intel MSRs. Some also available on other CPUs */ 57*98568f0fSGraeme Russ #define MSR_IA32_PERFCTR0 0x000000c1 58*98568f0fSGraeme Russ #define MSR_IA32_PERFCTR1 0x000000c2 59*98568f0fSGraeme Russ #define MSR_FSB_FREQ 0x000000cd 60*98568f0fSGraeme Russ 61*98568f0fSGraeme Russ #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 62*98568f0fSGraeme Russ #define NHM_C3_AUTO_DEMOTE (1UL << 25) 63*98568f0fSGraeme Russ #define NHM_C1_AUTO_DEMOTE (1UL << 26) 64*98568f0fSGraeme Russ #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 65*98568f0fSGraeme Russ 66*98568f0fSGraeme Russ #define MSR_MTRRcap 0x000000fe 67*98568f0fSGraeme Russ #define MSR_IA32_BBL_CR_CTL 0x00000119 68*98568f0fSGraeme Russ #define MSR_IA32_BBL_CR_CTL3 0x0000011e 69*98568f0fSGraeme Russ 70*98568f0fSGraeme Russ #define MSR_IA32_SYSENTER_CS 0x00000174 71*98568f0fSGraeme Russ #define MSR_IA32_SYSENTER_ESP 0x00000175 72*98568f0fSGraeme Russ #define MSR_IA32_SYSENTER_EIP 0x00000176 73*98568f0fSGraeme Russ 74*98568f0fSGraeme Russ #define MSR_IA32_MCG_CAP 0x00000179 75*98568f0fSGraeme Russ #define MSR_IA32_MCG_STATUS 0x0000017a 76*98568f0fSGraeme Russ #define MSR_IA32_MCG_CTL 0x0000017b 77*98568f0fSGraeme Russ 78*98568f0fSGraeme Russ #define MSR_OFFCORE_RSP_0 0x000001a6 79*98568f0fSGraeme Russ #define MSR_OFFCORE_RSP_1 0x000001a7 80*98568f0fSGraeme Russ 81*98568f0fSGraeme Russ #define MSR_IA32_PEBS_ENABLE 0x000003f1 82*98568f0fSGraeme Russ #define MSR_IA32_DS_AREA 0x00000600 83*98568f0fSGraeme Russ #define MSR_IA32_PERF_CAPABILITIES 0x00000345 84*98568f0fSGraeme Russ 85*98568f0fSGraeme Russ #define MSR_MTRRfix64K_00000 0x00000250 86*98568f0fSGraeme Russ #define MSR_MTRRfix16K_80000 0x00000258 87*98568f0fSGraeme Russ #define MSR_MTRRfix16K_A0000 0x00000259 88*98568f0fSGraeme Russ #define MSR_MTRRfix4K_C0000 0x00000268 89*98568f0fSGraeme Russ #define MSR_MTRRfix4K_C8000 0x00000269 90*98568f0fSGraeme Russ #define MSR_MTRRfix4K_D0000 0x0000026a 91*98568f0fSGraeme Russ #define MSR_MTRRfix4K_D8000 0x0000026b 92*98568f0fSGraeme Russ #define MSR_MTRRfix4K_E0000 0x0000026c 93*98568f0fSGraeme Russ #define MSR_MTRRfix4K_E8000 0x0000026d 94*98568f0fSGraeme Russ #define MSR_MTRRfix4K_F0000 0x0000026e 95*98568f0fSGraeme Russ #define MSR_MTRRfix4K_F8000 0x0000026f 96*98568f0fSGraeme Russ #define MSR_MTRRdefType 0x000002ff 97*98568f0fSGraeme Russ 98*98568f0fSGraeme Russ #define MSR_IA32_CR_PAT 0x00000277 99*98568f0fSGraeme Russ 100*98568f0fSGraeme Russ #define MSR_IA32_DEBUGCTLMSR 0x000001d9 101*98568f0fSGraeme Russ #define MSR_IA32_LASTBRANCHFROMIP 0x000001db 102*98568f0fSGraeme Russ #define MSR_IA32_LASTBRANCHTOIP 0x000001dc 103*98568f0fSGraeme Russ #define MSR_IA32_LASTINTFROMIP 0x000001dd 104*98568f0fSGraeme Russ #define MSR_IA32_LASTINTTOIP 0x000001de 105*98568f0fSGraeme Russ 106*98568f0fSGraeme Russ /* DEBUGCTLMSR bits (others vary by model): */ 107*98568f0fSGraeme Russ #define DEBUGCTLMSR_LBR (1UL << 0) 108*98568f0fSGraeme Russ #define DEBUGCTLMSR_BTF (1UL << 1) 109*98568f0fSGraeme Russ #define DEBUGCTLMSR_TR (1UL << 6) 110*98568f0fSGraeme Russ #define DEBUGCTLMSR_BTS (1UL << 7) 111*98568f0fSGraeme Russ #define DEBUGCTLMSR_BTINT (1UL << 8) 112*98568f0fSGraeme Russ #define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 113*98568f0fSGraeme Russ #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 114*98568f0fSGraeme Russ #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 115*98568f0fSGraeme Russ 116*98568f0fSGraeme Russ #define MSR_IA32_MC0_CTL 0x00000400 117*98568f0fSGraeme Russ #define MSR_IA32_MC0_STATUS 0x00000401 118*98568f0fSGraeme Russ #define MSR_IA32_MC0_ADDR 0x00000402 119*98568f0fSGraeme Russ #define MSR_IA32_MC0_MISC 0x00000403 120*98568f0fSGraeme Russ 121*98568f0fSGraeme Russ #define MSR_AMD64_MC0_MASK 0xc0010044 122*98568f0fSGraeme Russ 123*98568f0fSGraeme Russ #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 124*98568f0fSGraeme Russ #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 125*98568f0fSGraeme Russ #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 126*98568f0fSGraeme Russ #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 127*98568f0fSGraeme Russ 128*98568f0fSGraeme Russ #define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 129*98568f0fSGraeme Russ 130*98568f0fSGraeme Russ /* These are consecutive and not in the normal 4er MCE bank block */ 131*98568f0fSGraeme Russ #define MSR_IA32_MC0_CTL2 0x00000280 132*98568f0fSGraeme Russ #define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 133*98568f0fSGraeme Russ 134*98568f0fSGraeme Russ #define MSR_P6_PERFCTR0 0x000000c1 135*98568f0fSGraeme Russ #define MSR_P6_PERFCTR1 0x000000c2 136*98568f0fSGraeme Russ #define MSR_P6_EVNTSEL0 0x00000186 137*98568f0fSGraeme Russ #define MSR_P6_EVNTSEL1 0x00000187 138*98568f0fSGraeme Russ 139*98568f0fSGraeme Russ /* AMD64 MSRs. Not complete. See the architecture manual for a more 140*98568f0fSGraeme Russ complete list. */ 141*98568f0fSGraeme Russ 142*98568f0fSGraeme Russ #define MSR_AMD64_PATCH_LEVEL 0x0000008b 143*98568f0fSGraeme Russ #define MSR_AMD64_NB_CFG 0xc001001f 144*98568f0fSGraeme Russ #define MSR_AMD64_PATCH_LOADER 0xc0010020 145*98568f0fSGraeme Russ #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 146*98568f0fSGraeme Russ #define MSR_AMD64_OSVW_STATUS 0xc0010141 147*98568f0fSGraeme Russ #define MSR_AMD64_DC_CFG 0xc0011022 148*98568f0fSGraeme Russ #define MSR_AMD64_IBSFETCHCTL 0xc0011030 149*98568f0fSGraeme Russ #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 150*98568f0fSGraeme Russ #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 151*98568f0fSGraeme Russ #define MSR_AMD64_IBSOPCTL 0xc0011033 152*98568f0fSGraeme Russ #define MSR_AMD64_IBSOPRIP 0xc0011034 153*98568f0fSGraeme Russ #define MSR_AMD64_IBSOPDATA 0xc0011035 154*98568f0fSGraeme Russ #define MSR_AMD64_IBSOPDATA2 0xc0011036 155*98568f0fSGraeme Russ #define MSR_AMD64_IBSOPDATA3 0xc0011037 156*98568f0fSGraeme Russ #define MSR_AMD64_IBSDCLINAD 0xc0011038 157*98568f0fSGraeme Russ #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 158*98568f0fSGraeme Russ #define MSR_AMD64_IBSCTL 0xc001103a 159*98568f0fSGraeme Russ #define MSR_AMD64_IBSBRTARGET 0xc001103b 160*98568f0fSGraeme Russ 161*98568f0fSGraeme Russ /* Fam 15h MSRs */ 162*98568f0fSGraeme Russ #define MSR_F15H_PERF_CTL 0xc0010200 163*98568f0fSGraeme Russ #define MSR_F15H_PERF_CTR 0xc0010201 164*98568f0fSGraeme Russ 165*98568f0fSGraeme Russ /* Fam 10h MSRs */ 166*98568f0fSGraeme Russ #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 167*98568f0fSGraeme Russ #define FAM10H_MMIO_CONF_ENABLE (1<<0) 168*98568f0fSGraeme Russ #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 169*98568f0fSGraeme Russ #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 170*98568f0fSGraeme Russ #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 171*98568f0fSGraeme Russ #define FAM10H_MMIO_CONF_BASE_SHIFT 20 172*98568f0fSGraeme Russ #define MSR_FAM10H_NODE_ID 0xc001100c 173*98568f0fSGraeme Russ 174*98568f0fSGraeme Russ /* K8 MSRs */ 175*98568f0fSGraeme Russ #define MSR_K8_TOP_MEM1 0xc001001a 176*98568f0fSGraeme Russ #define MSR_K8_TOP_MEM2 0xc001001d 177*98568f0fSGraeme Russ #define MSR_K8_SYSCFG 0xc0010010 178*98568f0fSGraeme Russ #define MSR_K8_INT_PENDING_MSG 0xc0010055 179*98568f0fSGraeme Russ /* C1E active bits in int pending message */ 180*98568f0fSGraeme Russ #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 181*98568f0fSGraeme Russ #define MSR_K8_TSEG_ADDR 0xc0010112 182*98568f0fSGraeme Russ #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 183*98568f0fSGraeme Russ #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 184*98568f0fSGraeme Russ #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 185*98568f0fSGraeme Russ 186*98568f0fSGraeme Russ /* K7 MSRs */ 187*98568f0fSGraeme Russ #define MSR_K7_EVNTSEL0 0xc0010000 188*98568f0fSGraeme Russ #define MSR_K7_PERFCTR0 0xc0010004 189*98568f0fSGraeme Russ #define MSR_K7_EVNTSEL1 0xc0010001 190*98568f0fSGraeme Russ #define MSR_K7_PERFCTR1 0xc0010005 191*98568f0fSGraeme Russ #define MSR_K7_EVNTSEL2 0xc0010002 192*98568f0fSGraeme Russ #define MSR_K7_PERFCTR2 0xc0010006 193*98568f0fSGraeme Russ #define MSR_K7_EVNTSEL3 0xc0010003 194*98568f0fSGraeme Russ #define MSR_K7_PERFCTR3 0xc0010007 195*98568f0fSGraeme Russ #define MSR_K7_CLK_CTL 0xc001001b 196*98568f0fSGraeme Russ #define MSR_K7_HWCR 0xc0010015 197*98568f0fSGraeme Russ #define MSR_K7_FID_VID_CTL 0xc0010041 198*98568f0fSGraeme Russ #define MSR_K7_FID_VID_STATUS 0xc0010042 199*98568f0fSGraeme Russ 200*98568f0fSGraeme Russ /* K6 MSRs */ 201*98568f0fSGraeme Russ #define MSR_K6_WHCR 0xc0000082 202*98568f0fSGraeme Russ #define MSR_K6_UWCCR 0xc0000085 203*98568f0fSGraeme Russ #define MSR_K6_EPMR 0xc0000086 204*98568f0fSGraeme Russ #define MSR_K6_PSOR 0xc0000087 205*98568f0fSGraeme Russ #define MSR_K6_PFIR 0xc0000088 206*98568f0fSGraeme Russ 207*98568f0fSGraeme Russ /* Centaur-Hauls/IDT defined MSRs. */ 208*98568f0fSGraeme Russ #define MSR_IDT_FCR1 0x00000107 209*98568f0fSGraeme Russ #define MSR_IDT_FCR2 0x00000108 210*98568f0fSGraeme Russ #define MSR_IDT_FCR3 0x00000109 211*98568f0fSGraeme Russ #define MSR_IDT_FCR4 0x0000010a 212*98568f0fSGraeme Russ 213*98568f0fSGraeme Russ #define MSR_IDT_MCR0 0x00000110 214*98568f0fSGraeme Russ #define MSR_IDT_MCR1 0x00000111 215*98568f0fSGraeme Russ #define MSR_IDT_MCR2 0x00000112 216*98568f0fSGraeme Russ #define MSR_IDT_MCR3 0x00000113 217*98568f0fSGraeme Russ #define MSR_IDT_MCR4 0x00000114 218*98568f0fSGraeme Russ #define MSR_IDT_MCR5 0x00000115 219*98568f0fSGraeme Russ #define MSR_IDT_MCR6 0x00000116 220*98568f0fSGraeme Russ #define MSR_IDT_MCR7 0x00000117 221*98568f0fSGraeme Russ #define MSR_IDT_MCR_CTRL 0x00000120 222*98568f0fSGraeme Russ 223*98568f0fSGraeme Russ /* VIA Cyrix defined MSRs*/ 224*98568f0fSGraeme Russ #define MSR_VIA_FCR 0x00001107 225*98568f0fSGraeme Russ #define MSR_VIA_LONGHAUL 0x0000110a 226*98568f0fSGraeme Russ #define MSR_VIA_RNG 0x0000110b 227*98568f0fSGraeme Russ #define MSR_VIA_BCR2 0x00001147 228*98568f0fSGraeme Russ 229*98568f0fSGraeme Russ /* Transmeta defined MSRs */ 230*98568f0fSGraeme Russ #define MSR_TMTA_LONGRUN_CTRL 0x80868010 231*98568f0fSGraeme Russ #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 232*98568f0fSGraeme Russ #define MSR_TMTA_LRTI_READOUT 0x80868018 233*98568f0fSGraeme Russ #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 234*98568f0fSGraeme Russ 235*98568f0fSGraeme Russ /* Intel defined MSRs. */ 236*98568f0fSGraeme Russ #define MSR_IA32_P5_MC_ADDR 0x00000000 237*98568f0fSGraeme Russ #define MSR_IA32_P5_MC_TYPE 0x00000001 238*98568f0fSGraeme Russ #define MSR_IA32_TSC 0x00000010 239*98568f0fSGraeme Russ #define MSR_IA32_PLATFORM_ID 0x00000017 240*98568f0fSGraeme Russ #define MSR_IA32_EBL_CR_POWERON 0x0000002a 241*98568f0fSGraeme Russ #define MSR_EBC_FREQUENCY_ID 0x0000002c 242*98568f0fSGraeme Russ #define MSR_IA32_FEATURE_CONTROL 0x0000003a 243*98568f0fSGraeme Russ 244*98568f0fSGraeme Russ #define FEATURE_CONTROL_LOCKED (1<<0) 245*98568f0fSGraeme Russ #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) 246*98568f0fSGraeme Russ #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 247*98568f0fSGraeme Russ 248*98568f0fSGraeme Russ #define MSR_IA32_APICBASE 0x0000001b 249*98568f0fSGraeme Russ #define MSR_IA32_APICBASE_BSP (1<<8) 250*98568f0fSGraeme Russ #define MSR_IA32_APICBASE_ENABLE (1<<11) 251*98568f0fSGraeme Russ #define MSR_IA32_APICBASE_BASE (0xfffff<<12) 252*98568f0fSGraeme Russ 253*98568f0fSGraeme Russ #define MSR_IA32_UCODE_WRITE 0x00000079 254*98568f0fSGraeme Russ #define MSR_IA32_UCODE_REV 0x0000008b 255*98568f0fSGraeme Russ 256*98568f0fSGraeme Russ #define MSR_IA32_PERF_STATUS 0x00000198 257*98568f0fSGraeme Russ #define MSR_IA32_PERF_CTL 0x00000199 258*98568f0fSGraeme Russ 259*98568f0fSGraeme Russ #define MSR_IA32_MPERF 0x000000e7 260*98568f0fSGraeme Russ #define MSR_IA32_APERF 0x000000e8 261*98568f0fSGraeme Russ 262*98568f0fSGraeme Russ #define MSR_IA32_THERM_CONTROL 0x0000019a 263*98568f0fSGraeme Russ #define MSR_IA32_THERM_INTERRUPT 0x0000019b 264*98568f0fSGraeme Russ 265*98568f0fSGraeme Russ #define THERM_INT_HIGH_ENABLE (1 << 0) 266*98568f0fSGraeme Russ #define THERM_INT_LOW_ENABLE (1 << 1) 267*98568f0fSGraeme Russ #define THERM_INT_PLN_ENABLE (1 << 24) 268*98568f0fSGraeme Russ 269*98568f0fSGraeme Russ #define MSR_IA32_THERM_STATUS 0x0000019c 270*98568f0fSGraeme Russ 271*98568f0fSGraeme Russ #define THERM_STATUS_PROCHOT (1 << 0) 272*98568f0fSGraeme Russ #define THERM_STATUS_POWER_LIMIT (1 << 10) 273*98568f0fSGraeme Russ 274*98568f0fSGraeme Russ #define MSR_THERM2_CTL 0x0000019d 275*98568f0fSGraeme Russ 276*98568f0fSGraeme Russ #define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 277*98568f0fSGraeme Russ 278*98568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE 0x000001a0 279*98568f0fSGraeme Russ 280*98568f0fSGraeme Russ #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 281*98568f0fSGraeme Russ 282*98568f0fSGraeme Russ #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 283*98568f0fSGraeme Russ 284*98568f0fSGraeme Russ #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 285*98568f0fSGraeme Russ 286*98568f0fSGraeme Russ #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 287*98568f0fSGraeme Russ #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 288*98568f0fSGraeme Russ 289*98568f0fSGraeme Russ #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 290*98568f0fSGraeme Russ 291*98568f0fSGraeme Russ #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 292*98568f0fSGraeme Russ #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 293*98568f0fSGraeme Russ #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 294*98568f0fSGraeme Russ 295*98568f0fSGraeme Russ /* Thermal Thresholds Support */ 296*98568f0fSGraeme Russ #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 297*98568f0fSGraeme Russ #define THERM_SHIFT_THRESHOLD0 8 298*98568f0fSGraeme Russ #define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 299*98568f0fSGraeme Russ #define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 300*98568f0fSGraeme Russ #define THERM_SHIFT_THRESHOLD1 16 301*98568f0fSGraeme Russ #define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 302*98568f0fSGraeme Russ #define THERM_STATUS_THRESHOLD0 (1 << 6) 303*98568f0fSGraeme Russ #define THERM_LOG_THRESHOLD0 (1 << 7) 304*98568f0fSGraeme Russ #define THERM_STATUS_THRESHOLD1 (1 << 8) 305*98568f0fSGraeme Russ #define THERM_LOG_THRESHOLD1 (1 << 9) 306*98568f0fSGraeme Russ 307*98568f0fSGraeme Russ /* MISC_ENABLE bits: architectural */ 308*98568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0) 309*98568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1) 310*98568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_EMON (1ULL << 7) 311*98568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11) 312*98568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12) 313*98568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16) 314*98568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18) 315*98568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << 22) 316*98568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << 23) 317*98568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34) 318*98568f0fSGraeme Russ 319*98568f0fSGraeme Russ /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 320*98568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << 2) 321*98568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_TM1 (1ULL << 3) 322*98568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4) 323*98568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << 6) 324*98568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << 8) 325*98568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << 9) 326*98568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_FERR (1ULL << 10) 327*98568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << 10) 328*98568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_TM2 (1ULL << 13) 329*98568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << 19) 330*98568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << 20) 331*98568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << 24) 332*98568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << 37) 333*98568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38) 334*98568f0fSGraeme Russ #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39) 335*98568f0fSGraeme Russ 336*98568f0fSGraeme Russ /* P4/Xeon+ specific */ 337*98568f0fSGraeme Russ #define MSR_IA32_MCG_EAX 0x00000180 338*98568f0fSGraeme Russ #define MSR_IA32_MCG_EBX 0x00000181 339*98568f0fSGraeme Russ #define MSR_IA32_MCG_ECX 0x00000182 340*98568f0fSGraeme Russ #define MSR_IA32_MCG_EDX 0x00000183 341*98568f0fSGraeme Russ #define MSR_IA32_MCG_ESI 0x00000184 342*98568f0fSGraeme Russ #define MSR_IA32_MCG_EDI 0x00000185 343*98568f0fSGraeme Russ #define MSR_IA32_MCG_EBP 0x00000186 344*98568f0fSGraeme Russ #define MSR_IA32_MCG_ESP 0x00000187 345*98568f0fSGraeme Russ #define MSR_IA32_MCG_EFLAGS 0x00000188 346*98568f0fSGraeme Russ #define MSR_IA32_MCG_EIP 0x00000189 347*98568f0fSGraeme Russ #define MSR_IA32_MCG_RESERVED 0x0000018a 348*98568f0fSGraeme Russ 349*98568f0fSGraeme Russ /* Pentium IV performance counter MSRs */ 350*98568f0fSGraeme Russ #define MSR_P4_BPU_PERFCTR0 0x00000300 351*98568f0fSGraeme Russ #define MSR_P4_BPU_PERFCTR1 0x00000301 352*98568f0fSGraeme Russ #define MSR_P4_BPU_PERFCTR2 0x00000302 353*98568f0fSGraeme Russ #define MSR_P4_BPU_PERFCTR3 0x00000303 354*98568f0fSGraeme Russ #define MSR_P4_MS_PERFCTR0 0x00000304 355*98568f0fSGraeme Russ #define MSR_P4_MS_PERFCTR1 0x00000305 356*98568f0fSGraeme Russ #define MSR_P4_MS_PERFCTR2 0x00000306 357*98568f0fSGraeme Russ #define MSR_P4_MS_PERFCTR3 0x00000307 358*98568f0fSGraeme Russ #define MSR_P4_FLAME_PERFCTR0 0x00000308 359*98568f0fSGraeme Russ #define MSR_P4_FLAME_PERFCTR1 0x00000309 360*98568f0fSGraeme Russ #define MSR_P4_FLAME_PERFCTR2 0x0000030a 361*98568f0fSGraeme Russ #define MSR_P4_FLAME_PERFCTR3 0x0000030b 362*98568f0fSGraeme Russ #define MSR_P4_IQ_PERFCTR0 0x0000030c 363*98568f0fSGraeme Russ #define MSR_P4_IQ_PERFCTR1 0x0000030d 364*98568f0fSGraeme Russ #define MSR_P4_IQ_PERFCTR2 0x0000030e 365*98568f0fSGraeme Russ #define MSR_P4_IQ_PERFCTR3 0x0000030f 366*98568f0fSGraeme Russ #define MSR_P4_IQ_PERFCTR4 0x00000310 367*98568f0fSGraeme Russ #define MSR_P4_IQ_PERFCTR5 0x00000311 368*98568f0fSGraeme Russ #define MSR_P4_BPU_CCCR0 0x00000360 369*98568f0fSGraeme Russ #define MSR_P4_BPU_CCCR1 0x00000361 370*98568f0fSGraeme Russ #define MSR_P4_BPU_CCCR2 0x00000362 371*98568f0fSGraeme Russ #define MSR_P4_BPU_CCCR3 0x00000363 372*98568f0fSGraeme Russ #define MSR_P4_MS_CCCR0 0x00000364 373*98568f0fSGraeme Russ #define MSR_P4_MS_CCCR1 0x00000365 374*98568f0fSGraeme Russ #define MSR_P4_MS_CCCR2 0x00000366 375*98568f0fSGraeme Russ #define MSR_P4_MS_CCCR3 0x00000367 376*98568f0fSGraeme Russ #define MSR_P4_FLAME_CCCR0 0x00000368 377*98568f0fSGraeme Russ #define MSR_P4_FLAME_CCCR1 0x00000369 378*98568f0fSGraeme Russ #define MSR_P4_FLAME_CCCR2 0x0000036a 379*98568f0fSGraeme Russ #define MSR_P4_FLAME_CCCR3 0x0000036b 380*98568f0fSGraeme Russ #define MSR_P4_IQ_CCCR0 0x0000036c 381*98568f0fSGraeme Russ #define MSR_P4_IQ_CCCR1 0x0000036d 382*98568f0fSGraeme Russ #define MSR_P4_IQ_CCCR2 0x0000036e 383*98568f0fSGraeme Russ #define MSR_P4_IQ_CCCR3 0x0000036f 384*98568f0fSGraeme Russ #define MSR_P4_IQ_CCCR4 0x00000370 385*98568f0fSGraeme Russ #define MSR_P4_IQ_CCCR5 0x00000371 386*98568f0fSGraeme Russ #define MSR_P4_ALF_ESCR0 0x000003ca 387*98568f0fSGraeme Russ #define MSR_P4_ALF_ESCR1 0x000003cb 388*98568f0fSGraeme Russ #define MSR_P4_BPU_ESCR0 0x000003b2 389*98568f0fSGraeme Russ #define MSR_P4_BPU_ESCR1 0x000003b3 390*98568f0fSGraeme Russ #define MSR_P4_BSU_ESCR0 0x000003a0 391*98568f0fSGraeme Russ #define MSR_P4_BSU_ESCR1 0x000003a1 392*98568f0fSGraeme Russ #define MSR_P4_CRU_ESCR0 0x000003b8 393*98568f0fSGraeme Russ #define MSR_P4_CRU_ESCR1 0x000003b9 394*98568f0fSGraeme Russ #define MSR_P4_CRU_ESCR2 0x000003cc 395*98568f0fSGraeme Russ #define MSR_P4_CRU_ESCR3 0x000003cd 396*98568f0fSGraeme Russ #define MSR_P4_CRU_ESCR4 0x000003e0 397*98568f0fSGraeme Russ #define MSR_P4_CRU_ESCR5 0x000003e1 398*98568f0fSGraeme Russ #define MSR_P4_DAC_ESCR0 0x000003a8 399*98568f0fSGraeme Russ #define MSR_P4_DAC_ESCR1 0x000003a9 400*98568f0fSGraeme Russ #define MSR_P4_FIRM_ESCR0 0x000003a4 401*98568f0fSGraeme Russ #define MSR_P4_FIRM_ESCR1 0x000003a5 402*98568f0fSGraeme Russ #define MSR_P4_FLAME_ESCR0 0x000003a6 403*98568f0fSGraeme Russ #define MSR_P4_FLAME_ESCR1 0x000003a7 404*98568f0fSGraeme Russ #define MSR_P4_FSB_ESCR0 0x000003a2 405*98568f0fSGraeme Russ #define MSR_P4_FSB_ESCR1 0x000003a3 406*98568f0fSGraeme Russ #define MSR_P4_IQ_ESCR0 0x000003ba 407*98568f0fSGraeme Russ #define MSR_P4_IQ_ESCR1 0x000003bb 408*98568f0fSGraeme Russ #define MSR_P4_IS_ESCR0 0x000003b4 409*98568f0fSGraeme Russ #define MSR_P4_IS_ESCR1 0x000003b5 410*98568f0fSGraeme Russ #define MSR_P4_ITLB_ESCR0 0x000003b6 411*98568f0fSGraeme Russ #define MSR_P4_ITLB_ESCR1 0x000003b7 412*98568f0fSGraeme Russ #define MSR_P4_IX_ESCR0 0x000003c8 413*98568f0fSGraeme Russ #define MSR_P4_IX_ESCR1 0x000003c9 414*98568f0fSGraeme Russ #define MSR_P4_MOB_ESCR0 0x000003aa 415*98568f0fSGraeme Russ #define MSR_P4_MOB_ESCR1 0x000003ab 416*98568f0fSGraeme Russ #define MSR_P4_MS_ESCR0 0x000003c0 417*98568f0fSGraeme Russ #define MSR_P4_MS_ESCR1 0x000003c1 418*98568f0fSGraeme Russ #define MSR_P4_PMH_ESCR0 0x000003ac 419*98568f0fSGraeme Russ #define MSR_P4_PMH_ESCR1 0x000003ad 420*98568f0fSGraeme Russ #define MSR_P4_RAT_ESCR0 0x000003bc 421*98568f0fSGraeme Russ #define MSR_P4_RAT_ESCR1 0x000003bd 422*98568f0fSGraeme Russ #define MSR_P4_SAAT_ESCR0 0x000003ae 423*98568f0fSGraeme Russ #define MSR_P4_SAAT_ESCR1 0x000003af 424*98568f0fSGraeme Russ #define MSR_P4_SSU_ESCR0 0x000003be 425*98568f0fSGraeme Russ #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 426*98568f0fSGraeme Russ 427*98568f0fSGraeme Russ #define MSR_P4_TBPU_ESCR0 0x000003c2 428*98568f0fSGraeme Russ #define MSR_P4_TBPU_ESCR1 0x000003c3 429*98568f0fSGraeme Russ #define MSR_P4_TC_ESCR0 0x000003c4 430*98568f0fSGraeme Russ #define MSR_P4_TC_ESCR1 0x000003c5 431*98568f0fSGraeme Russ #define MSR_P4_U2L_ESCR0 0x000003b0 432*98568f0fSGraeme Russ #define MSR_P4_U2L_ESCR1 0x000003b1 433*98568f0fSGraeme Russ 434*98568f0fSGraeme Russ #define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 435*98568f0fSGraeme Russ 436*98568f0fSGraeme Russ /* Intel Core-based CPU performance counters */ 437*98568f0fSGraeme Russ #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 438*98568f0fSGraeme Russ #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 439*98568f0fSGraeme Russ #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 440*98568f0fSGraeme Russ #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 441*98568f0fSGraeme Russ #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 442*98568f0fSGraeme Russ #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 443*98568f0fSGraeme Russ #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 444*98568f0fSGraeme Russ 445*98568f0fSGraeme Russ /* Geode defined MSRs */ 446*98568f0fSGraeme Russ #define MSR_GEODE_BUSCONT_CONF0 0x00001900 447*98568f0fSGraeme Russ 448*98568f0fSGraeme Russ /* Intel VT MSRs */ 449*98568f0fSGraeme Russ #define MSR_IA32_VMX_BASIC 0x00000480 450*98568f0fSGraeme Russ #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 451*98568f0fSGraeme Russ #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 452*98568f0fSGraeme Russ #define MSR_IA32_VMX_EXIT_CTLS 0x00000483 453*98568f0fSGraeme Russ #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 454*98568f0fSGraeme Russ #define MSR_IA32_VMX_MISC 0x00000485 455*98568f0fSGraeme Russ #define MSR_IA32_VMX_CR0_FIXED0 0x00000486 456*98568f0fSGraeme Russ #define MSR_IA32_VMX_CR0_FIXED1 0x00000487 457*98568f0fSGraeme Russ #define MSR_IA32_VMX_CR4_FIXED0 0x00000488 458*98568f0fSGraeme Russ #define MSR_IA32_VMX_CR4_FIXED1 0x00000489 459*98568f0fSGraeme Russ #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 460*98568f0fSGraeme Russ #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 461*98568f0fSGraeme Russ #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 462*98568f0fSGraeme Russ 463*98568f0fSGraeme Russ /* AMD-V MSRs */ 464*98568f0fSGraeme Russ 465*98568f0fSGraeme Russ #define MSR_VM_CR 0xc0010114 466*98568f0fSGraeme Russ #define MSR_VM_IGNNE 0xc0010115 467*98568f0fSGraeme Russ #define MSR_VM_HSAVE_PA 0xc0010117 468*98568f0fSGraeme Russ 469*98568f0fSGraeme Russ #endif /* _ASM_X86_MSR_INDEX_H */ 470